help with write to fpga function

Discussion in 'VHDL' started by thomas, Oct 12, 2004.

  1. thomas

    thomas Guest

    Hi

    I am going to write a program in vhdl that can handle 5 write cycles to
    one address
    something like this

    data_reg is a array from 0 to 2 of 8 bits
    address is 5 bits
    data is 8bits

    if cs = 1 then
    if not_we = 0 then
    if address = "00001" :
    data_reg(1)(index) <= data;
    index = index +1;
    elsif address = "00010" :
    data_reg(2)(index) <= data;
    index = index +1;
    elsif address = "00011" :
    data_reg(3)(index) <= data;
    index = index +1;

    ......
    end if
    end if
    end if

    what the data in data_reg to be latch out when the index is 2

    is there a god way of doing this

    is there something i can read about this ???
    --
    thomas
     
    thomas, Oct 12, 2004
    #1
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