Help !!!

Discussion in 'VHDL' started by Abhishek Kumar, Jul 2, 2003.

  1. hi
    When I ran a vhdl code and saw the place and route report in the
    Xilinx ISE after constraining the time constraint to 20ns,I
    wasn't getting the Actual pad to pad delay in the report !!
    It was like :

    --------------------------------------------------------------------------------
    Constraint | Requested | Actual
    | Logic
    | |
    | Levels
    --------------------------------------------------------------------------------
    TS_P3P = MAXDELAY FROM TIMEGRP "PADS" TO | |
    |
    TIMEGRP "PADS" 20 nS | |
    |
    --------------------------------------------------------------------------------


    The requested as well as the Actual delay were absent !!

    Can someone please help me !!!

    very best regards
    abhishek
     
    Abhishek Kumar, Jul 2, 2003
    #1
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