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Discussion in 'VHDL' started by craigs2, Mar 16, 2006.

  1. craigs2

    craigs2

    Joined:
    Mar 16, 2006
    Messages:
    3
    Hi there,
    Really struggling with some VHDL code. Have been asked to write a high level VHDL model of a 16-word by 12 bit memory in which the contents of the memory are initialised by reading from a file.

    The memory should have 5 address lines, 12 bi-directional, trisate data and an active low enable control. When enable is low the memory will read or write in accordance with the state of the read/write control. The read/write input is a single bit, 1 indicating read and 0 indicating write.

    Any help would be great, really struggling here chaps.
     
    craigs2, Mar 16, 2006
    #1
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