help

Discussion in 'VHDL' started by yoogy, Jun 27, 2010.

  1. yoogy

    yoogy

    Joined:
    Jun 27, 2010
    Messages:
    3
    hello,
    I have a project to make a parity counter(counter that counts the ones in a bit vector) by using a function inside a package..I want to make a test bench for this function but I can't...so may anyone please help me?
    here is the programe

    PACKAGE package_functions IS
    FUNCTION parity (a: bit_vector) RETURN bit;
    END PACKAGE package_functions;

    PACKAGE BODY package_functions IS
    FUNCTION parity (a: bit_vector) RETURN bit IS
    VARIABLE result: bit := '0'; -- default value
    BEGIN
    FOR i IN a'range LOOP
    result := result XOR a(i);
    END LOOP;
    RETURN result;
    END FUNCTION parity;
    END PACKAGE BODY package_functions;

    thanks in advanced.
    yoogy, Jun 27, 2010
    #1
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  2. yoogy

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    Uhm a test bench should provide inputs to the design being tested (the entity, which uses the listed package in your case)

    Enumerating all input values is impossible in most cases - though testing a reduced number of them, which should cover all "normal cases" with a number of inputs tested -- and especially also (hopefully all) "corner cases" being tested

    You didn't provide the entity/architecture implementation so it's kinda hard to say exactly how to test well; one can guess what your implementation might look like -- but hoping for people to guess at what you're doing makes it harder/more unlikely to get much help
    joris, Jun 27, 2010
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  3. yoogy

    yoogy

    Joined:
    Jun 27, 2010
    Messages:
    3
    ok thanks, but in general how can i test a function?
    yoogy, Jun 27, 2010
    #3
  4. yoogy

    yoogy

    Joined:
    Jun 27, 2010
    Messages:
    3
    i have made this programe but it keeps giving me errors
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;

    PACKAGE package_functions IS
    FUNCTION parity (a: std_logic_vector) RETURN bit;
    END PACKAGE package_functions;

    PACKAGE BODY package_functions IS
    FUNCTION parity (a: std_logic_vector) RETURN bit IS
    VARIABLE result: bit := '0'; -- default value
    BEGIN
    FOR i IN a'range LOOP
    result := result XOR a(i);
    END LOOP;
    RETURN result;
    END FUNCTION parity;
    END PACKAGE BODY package_functions;

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    Use work.package_functions.All ;

    Entity parity is
    port (A: in std_logic_vector ;
    B: out bit );
    End Entity parity ;

    Architecture test of parity is
    begin
    p1: process is
    begin

    B <= parity(A) ;
    End process p1 ;
    End Architecture test ;
    yoogy, Jun 27, 2010
    #4
  5. yoogy

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    I tried fixing some problems/errors in the code, resulting in this:
    Code:
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    
    PACKAGE package_functions IS
    FUNCTION f_parity (a: std_logic_vector) RETURN std_logic;
    END PACKAGE package_functions;
    
    PACKAGE BODY package_functions IS
    FUNCTION f_parity (a: std_logic_vector) RETURN std_logic IS
    VARIABLE result: std_logic := '0';
    BEGIN
    FOR i IN a'range LOOP
    result := result XOR a(i);
    END LOOP;
    RETURN result;
    END FUNCTION f_parity;
    END PACKAGE BODY package_functions;
    
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    Use work.package_functions.All ;
    
    Entity parity is
    generic(n : natural := 16);
    port (A: in std_logic_vector(n - 1 downto 0);
    B: out std_logic );
    End Entity parity ;
    
    Architecture test of parity is
    begin
    B <= f_parity(A) ;
    End Architecture test ;
    
    Then this might be a test bench (enumerating for a std_logic_vector of 4 bits)

    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.all, IEEE.Numeric_STD.all;
    
    entity parityTb is
    end parityTb;
    
    architecture test of parityTb is
      component parity is
        generic(n : natural := 16);
        port (A: in std_logic_vector(n - 1 downto 0);
        B: out std_logic );
      end component;
    
      constant n : natural := 4;
      signal A : std_logic_vector(n - 1 downto 0);
      signal B : std_logic;
    
      constant clock_period : time := 10 ns;
      constant reset_period : time := 100 ns;
    begin
    pmap: parity generic map(n => n)
                 port map(A => A, B => B);
      process is
        function calcParity(x : std_logic_vector) return std_logic is
          variable ret : std_logic := '0';
        begin
          for i in x'range loop
            if x(i) = '1' then
              ret := not ret;
            end if;
          end loop;
          return ret;
        end;
      begin
        wait for reset_period;
    
        for i in 0 to ((2**n)-1) loop
          A <= std_logic_vector(to_unsigned(i, n));
          wait for clock_period;
          assert B = calcParity(A) report "Got an incorrect parity" severity error;
        end loop;
    
        assert false report "Testbench finished" severity note;
        wait;
      end process;
    end test;
    
    I wrote a "simpler" function to evaluate the result; as the algorithm for parity is simple enough, writing another "more basic" function to test, might seem a bit stupid; however, (in general) if I'd be using exactly the same algorithm, errors in the implementation of the algorithm could go unnoticed.

    Note that enumerating for n=4 (or slightly larger) isn't a problem; n=31 would take very much time though!
    Last edited: Jun 27, 2010
    joris, Jun 27, 2010
    #5
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