hexa bus to decimal 7 segments - VHDL...

Discussion in 'VHDL' started by PC, Nov 10, 2003.

  1. PC

    PC Guest

    Please, anybody have some example to drive 3 displays 7 segments in decimal
    valur
    with bus of 8 bits in binarie value ...

    by example :
    if my bus is xFF, i want display 255 with my three digits ...

    thank's for any help
    Phil
    PC, Nov 10, 2003
    #1
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  2. I had a similar problem a while back and Peter Alfke replied with this bit
    of information (listed below). It worked great. Also Xilinx has a binary to
    bcd example on their website.

    Hope this helps

    Here is a time-proven hardware design for bit-serial binary to parallel
    BCD conversion. (I published this in 1973 in the Fairchild TTL
    Applications Handbook).

    Implement a bunch of 4-bit loadable shift register, but do not
    interconnect them.
    For each shift register drive a 4-bit adder (without carry in, but with
    carry output) from the 4 shift register outputs. Put a binary eleven (B)
    as other input on the adder.
    Connect the adder outputs to the shift register load inputs, but skewed
    one position downstream ( bit 0 of the adder drives bit 1 of the shift
    register ).
    Then use the carry output as load enable for "its" shift register, and
    also as input for the LSB of the downstream shift register ( both as
    shift- and as load- input)
    The S3 output ( most significant sum) goes nowhere. That's it.

    Shifting in binary data (MSB first) doubles the binary value on every
    shift. The adder monitors this and, on its carry output, signals that
    there is a value 5 or larger, which needs intervention: add 3 before the
    next shift ( which is equivalent to adding 6 after having shifted it)
    and load a carry into the next higher bit position.
    The neat trick is that the 4-bit adder simultaneously adds eleven to
    create a carry that detects the need for modification, and also adds
    three to do the modification.

    Shift in binary data, MSB first, and watch the BCD develop on the
    parallel shift register outputs. Note that BCD needs more bit positions
    than binary, so leave some headroom.
    Works like a champ, flawlessly since 30 years ago.

    Peter Alfke, no longer at Fairchild (but it was an interesting 10 years)
    "PC" <POUR ME REPONDRE :
    http://haltspam.free.fr/index.php?pseudo=philippe.chagny> wrote in message
    news:3faedf2b$0$10411$...
    > Please, anybody have some example to drive 3 displays 7 segments in

    decimal
    > valur
    > with bus of 8 bits in binarie value ...
    >
    > by example :
    > if my bus is xFF, i want display 255 with my three digits ...
    >
    > thank's for any help
    > Phil
    >
    >
    Jason Berringer, Nov 11, 2003
    #2
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  3. Jason,

    This is a whole lot smaller than the pyramid of binary to BCD converters
    that I remember seeing in my TTL application books. Great algorithm! I
    tried this out as a schematic in Quartus and it worked like a champ. I
    am definitely adding this to my bag'o'tricks.

    Marc

    Jason Berringer wrote:

    > Here is a time-proven hardware design for bit-serial binary to parallel
    > BCD conversion. (I published this in 1973 in the Fairchild TTL
    > Applications Handbook).
    Marc Guardiani, Nov 12, 2003
    #3
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