hi frnds

Discussion in 'VHDL' started by akanksha, Oct 7, 2009.

  1. akanksha

    akanksha

    Joined:
    Oct 7, 2009
    Messages:
    2
    hey ppl i am using xilinx core gnerator to generate a fifi version 3.3. i wanted to know how can i compile this hdl functionl model using modelsim.
    i have made a wrapper file(top level file for this fifo).

    1.in the hdl functional model it was mentioned tht i must compile the wrapper file before proceeding for behavioral simulation.could someone pls elaborate on this.

    2.how do i compile the xilinxcorelib??

    3.in the hdl functional model,which is obtained after generating the core what is the meaning of
    synthesis translate on/off???

    pls help me its really urgent.pls.
     
    akanksha, Oct 7, 2009
    #1
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