Hiding of subprogram designators

Discussion in 'VHDL' started by David Jones, Nov 17, 2003.

  1. David Jones

    David Jones Guest

    From VHDL-93 LRM section 10.3, page 144, lines 143-144:

    Within the specification of a subprogram, every declaration with the same
    designator as the subprogram is hidden. Where hidden in this manner, a
    declaration is visible neither by selection nor directly.

    Read one way, a subprogram declaration has the same designator as itself,
    therefore it should be hidden within the specification of the subprogram.
    As a consequence, it should not be possible to call a subprogram recursively.

    Casual experimentation with VHDL Simili indicates that this is not so (i.e.
    recursion is possible) and I would be surprised if recursion were not possible.

    If I try to overload a subprogram name as a signal, then I'm creating a
    homograph, and we already have rules to deal with that. If I try to overload
    a subprogram name as another subprogram, that works, and one overloaded
    subprogram can even call the other!

    Can someone clarify exactly what the spec is trying to prevent and why?
    David Jones, Nov 17, 2003
    #1
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  2. David Jones

    Alan Fitch Guest

    "David Jones" <> wrote in message
    news:XMbub.7149$...
    > From VHDL-93 LRM section 10.3, page 144, lines 143-144:
    >
    > Within the specification of a subprogram, every declaration with

    the same
    > designator as the subprogram is hidden. Where hidden in this

    manner, a
    > declaration is visible neither by selection nor directly.
    >
    > Read one way, a subprogram declaration has the same designator as

    itself,
    > therefore it should be hidden within the specification of the

    subprogram.
    > As a consequence, it should not be possible to call a subprogram

    recursively.
    >
    > Casual experimentation with VHDL Simili indicates that this is not

    so (i.e.
    > recursion is possible) and I would be surprised if recursion were

    not possible.
    >
    > If I try to overload a subprogram name as a signal, then I'm

    creating a
    > homograph, and we already have rules to deal with that. If I try to

    overload
    > a subprogram name as another subprogram, that works, and one

    overloaded
    > subprogram can even call the other!
    >
    > Can someone clarify exactly what the spec is trying to prevent and

    why?

    Hi David, as usual with the LRM you have to look up every phrase
    very carefully. The words "subprogram specification" refer to the
    the part of the subprogram from the start of it to the ';' or the 'is'
    i.e.

    procedure fred (variable A : in std_logic) ;
    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
    subprogram specification

    or

    impure function blob (constant A : BOOLEAN) return integer is
    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
    variable I : INTEGER;
    begin
    -- do something impure!

    return I

    end function;

    In other words, all it's saying is that you can't have a parameter
    with
    the same name as the subprogram, e.g.

    procedure fred (variable fred : in std_logic) is


    Have a look at section at the syntax summary in Annex A, p221, for
    a summary of what a subprogram specification is, or look in chapter
    2

    kind regards

    Alan

    P.S. There's no problem with recursion. In fact because declaration
    and body can be separated, it's possible to write mutually recursive
    procedures if you want to!

    --
    Alan Fitch
    Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
    Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
    1AW, UK
    Tel: +44 (0)1425 471223 mail:

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    http://www.doulos.com

    The contents of this message may contain personal views which are not
    the
    views of Doulos Ltd., unless specifically stated.
    Alan Fitch, Nov 18, 2003
    #2
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