hierarchical design with structural VHDL question

Discussion in 'VHDL' started by Neil Zanella, Oct 21, 2003.

  1. Neil Zanella

    Neil Zanella Guest

    Hello,

    I have several files, each file containing an entity and an
    architecture. Some entities have components comprised of entities
    which are defined together with their architectures in their
    own separate files. I would like to place collections of
    functionally related entities and architectures into the
    same file like I would in C. When I do this in VHDL, the
    sources no longer compile and I get completely incorrect
    warnings from the compiler (such as std_ulogic_vector
    being undefined despite the fact that I am including
    the appropriate ieee library and using ieee.std_logic_1164.all.

    Hence, may I ask, is it illegal to put more than one entity
    and architecture in the same file in VHDL, or is there something
    else that I am doing wrong?

    Thanks,

    Neil
     
    Neil Zanella, Oct 21, 2003
    #1
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  2. Neil Zanella

    Neil Zanella Guest

    Hello,

    The answer in this case is perhaps fairly straightforward. In VHDL, unlike
    in C, when you use the library and using statements they only apply to the
    entity and architecture which directly follows it. Hence such statements
    do not have file scope and must be included prior to the definition of
    every entity that makes use of them. Perhaps someone else will
    state this VHDL subtlety more formally / precisely.

    Thanks,

    Neil

    On Mon, 20 Oct 2003, Neil Zanella wrote:

    >
    > Hello,
    >
    > I have several files, each file containing an entity and an
    > architecture. Some entities have components comprised of entities
    > which are defined together with their architectures in their
    > own separate files. I would like to place collections of
    > functionally related entities and architectures into the
    > same file like I would in C. When I do this in VHDL, the
    > sources no longer compile and I get completely incorrect
    > warnings from the compiler (such as std_ulogic_vector
    > being undefined despite the fact that I am including
    > the appropriate ieee library and using ieee.std_logic_1164.all.
    >
    > Hence, may I ask, is it illegal to put more than one entity
    > and architecture in the same file in VHDL, or is there something
    > else that I am doing wrong?
    >
    > Thanks,
    >
    > Neil
     
    Neil Zanella, Oct 21, 2003
    #2
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  3. "Neil Zanella" <> wrote in message
    news:p...

    > I have several files, each file containing an entity and an
    > architecture. Some entities have components comprised of entities
    > which are defined together with their architectures in their
    > own separate files. I would like to place collections of
    > functionally related entities and architectures into the
    > same file like I would in C. When I do this in VHDL, the
    > sources no longer compile and I get completely incorrect
    > warnings from the compiler (such as std_ulogic_vector
    > being undefined despite the fact that I am including
    > the appropriate ieee library and using ieee.std_logic_1164.all.
    >
    > Hence, may I ask, is it illegal to put more than one entity
    > and architecture in the same file in VHDL, or is there something
    > else that I am doing wrong?


    No,it's entirely legal (although it is *not* legal to
    split any design unit across more than one file, BTW).
    Whether it's a good idea, I'm less sure.

    Your problem is almost certainly that you have not
    repeated the library and use clauses before each new entity
    declaration. If you're used to C, you probably think of
    "header files" that are textually included in the compile
    an therefore apply throughout compilation of the whole
    source file. By contrast, in VHDL, library and use
    clauses apply only to the immediately following design
    unit. They don't represent textual inclusion; their
    only effect is to make a collection of name definitions
    visible while the next design unit is compiled.

    Slightly surprisingy, it's *not* necessary to repeat
    the library and use clauses before an architecture.
    Architectures are "secondary design units" and they
    inherit all name visibility from their "primary design
    unit", i.e. their entity. Similarly, a package body
    inherits name visibility from its package.

    ~~~~~~~~~~~~~~~~~~~~~~~~

    Would it be churlish to point out that, amongst your
    considerable flurry of sometimes quite combative posts
    recently, we have seen hardly a word of thanks for the
    many helpful responses you've elicited?
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Oct 22, 2003
    #3
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