Hierarchies not the best for video pipelines

Discussion in 'VHDL' started by Brad Smallridge, May 20, 2005.

  1. Am I missing something? It seems that I am spending a lot of
    time passing variables from subordinate routines to the top level
    and then back down to the next subordinate routine where what
    I really want is to send data from one subroutine to the next in
    a pipeline fashion. Is there any way to do this?

    b r a d @ a i v i s i o n . c o m
     
    Brad Smallridge, May 20, 2005
    #1
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  2. Brad Smallridge wrote:
    > Am I missing something? It seems that I am spending a lot of
    > time passing variables from subordinate routines to the top level
    > and then back down to the next subordinate routine where what
    > I really want is to send data from one subroutine to the next in
    > a pipeline fashion.


    If you are talking about procedure scope
    in a testbench, see today's other threads.

    If you are talking about synthesis code,
    you can improve variable scope by
    declaring all closely related variable objects
    in the same clocked process.

    -- Mike Treseler
     
    Mike Treseler, May 21, 2005
    #2
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