high impedance in VHDL

[joris]

I usually use the std_logic type instead of bit, but I use it as "bits" anyway (as VHDL lacks support for don't care, and other values are mostly helpful for debugging)

There's one strange possible value, 'Z', described as high impedance. I kinda understand what it's supposed to do but I have no clue how one could use it in VHDL as-is. Could anyone show some examples of meaningful uses?

 

[jeppe]

Well - 3-state buffers normally used whenever you want's to drive a line (a BUS) with more the one driver (output).

I got this example with a SPI Master and Slave (should be slaves to make more sence) - If you got two or more independent slave then only one of them allowed to drive the MISO line, hence must it be controlled with a statement like this:

MISO <= Shreg(7) when SS='0' else 'Z';

the complete code can be seen here:http://www.jjmk.dk/MMMI/Exercises/05_Counters_Shreg/No6_SPI_UARTS/SPI/Ver2/index.htm

Hope it helped you
Jeppe

 

[Jacob Christ]

VHDL High Impediance

So I have a follow up question... I have some VHDL code with a couple of pins that are shared with a uC. I set the pins to in std_logic and they work as inputs but they seem to drive the uC pins. When the CPLD chip is blank the uC inputs work fine... huh...

entity msac002_lcd is
Port ( osc: in std_logic;
button1 : in std_logic;
button2 : in std_logic;
led0 : out std_logic;
led1 : out std_logic;
spi_cs : in std_logic;
spi_sclk : in std_logic;
spi_mosi : in std_logic;
lcd_register : out std_logic_vector(23 downto 0));
end msac002_lcd;

architecture Behavioral of msac002_lcd is
signal clkdiv : std_logic_vector(10 downto 0);
signal display_reg : std_logic_vector(23 downto 0);

--component spi_24bit_data_in
-- Port ( cs_cpld, sclk, mosi : in std_logic;
-- display_reg : inout std_logic_vector(23 downto 0)
-- );
--end component;
begin

-- Divide the master clock (1.832Mhz) down to a lower frequency,
-- and drive xc2led with a slower clock signal from the counter.
-- The xc2btn resets the counter; when pressed, the LED is off.
-- This clock divider and xc2btn assignment are all that is needed
-- for a basic XC2 board check.

process (osc, button1) begin
if button1 = '1' then
clkdiv <= "00000000000";
elsif osc = '1' and osc'Event then
clkdiv <= clkdiv + 1;
end if;
end process;
led0 <= not clkdiv(10);

led1 <= button2;

--SPI: spi_24bit_data_in
-- port map ( spi_cs, spi_sclk, spi_mosi, display_reg(23 downto 0));

--shift mosi in to display_reg
process (spi_sclk, spi_cs) begin
if spi_cs = '0' then
if spi_sclk = '1' and spi_sclk'Event then
display_reg <= display_reg(22 downto 0) & spi_mosi; --shift left
end if;
else
lcd_register(23 downto 0) <= display_reg(23 downto 0);
end if;
end process;


end Behavioral;
Jacob

 

[jeppe]

Quick answer (hopefully)

In order to protect the circuit inside CPLD/FPGA's will a pin not be allowed to float - hence will there be a pull-up or pull-down resistor connected.

So if you connect two inputs, one of the CPLD pins and one of the uC pins will the CPLD pin properly drive you uC pin as well (this shouldn't be a problem) -or ????

Jeppe