How can i do combination logic in VHDL

Discussion in 'VHDL' started by Aiken, Sep 24, 2008.

  1. Aiken

    Aiken Guest

    I need to make a instruction decoder.
    the instruction_v is 32 bit.
    and I have 10 process will be command by the instruction.
    Input:
    instruction_v(31 downto 24) is command type
    instruction_v(23 downto 0) is the argument (some of the instruction
    don't need argument)

    Output:(they are NOT register, just wires)
    5 one bit std_logic , @ one for one simple instruction (only run/not
    run)
    5 std_logic_vector(n downto 0) (differnet instruction n will be
    different)

    My Question is,
    if I use "case" statement, in each case(one of the insturction), after
    I setup the correct instruction output, how can I set other output to
    be "zero"? do I need to do it in every cases? or?
    Aiken, Sep 24, 2008
    #1
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  2. Hi,

    On 24 Sep., 05:01, Aiken <> wrote:
    > I need to make a instruction decoder.

    [..]
    > Output:(they are NOT register, just wires)
    > 5 one bit std_logic , @ one for one simple instruction (only run/not
    > run)
    > 5 std_logic_vector(n downto 0) (differnet instruction n will be
    > different)
    >
    > My Question is,
    > if I use "case" statement, in each case(one of the insturction), after
    > I setup the correct instruction output, how can I set other output to
    > be "zero"? do I need to do it in every cases? or?


    USe the following template:
    process(all_process_inputs)
    Thomas Stanka, Sep 24, 2008
    #2
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  3. On 24 Sep., 05:01, Aiken <> wrote:
    > Input:
    > instruction_v(31 downto 24) is command type
    > instruction_v(23 downto 0) is the argument (some of the instruction
    > don't need argument)
    >
    > Output:(they are NOT register, just wires)
    > 5 one bit std_logic , @ one for one simple instruction (only run/not
    > run)
    > 5 std_logic_vector(n downto 0) (differnet instruction n will be
    > different)
    >
    > My Question is,
    > if I use "case" statement, in each case(one of the insturction), after
    > I setup the correct instruction output, how can I set other output to
    > be "zero"? do I need to do it in every cases? or?


    Hi,
    you can easily use the following style to set all outputs in a default
    value above the case and than switch only some outputs depending on
    the selections. All outputs that are not overwritten in the case will
    stay in their default value.

    process(<all_process_inputs>)
    <all_outputs> <= default_value
    case select_var
    when 1 =>
    <some_output> <= special_value
    when 2 =>
    <other_output> <= special_value
    ......

    Another option would be the way to look at the specific outputs in a
    concurrent statement.

    out1 <= '1' when <cond1> or <cond2> else
    '0'
    ......

    Both ways have their place and there are cases where the first way
    gives you a better readability of the code as the concurrent statement
    and sometimes your code would be more readable, when using the
    concurrent way.

    bye Thomas
    Thomas Stanka, Sep 24, 2008
    #3
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