How can I eliminate "Glitch"?

Discussion in 'VHDL' started by Jluis, May 5, 2004.

  1. Jluis

    Jluis Guest

    Hi everyone!!!! I program a big decoder, so the compilation is ok, but
    when I simulated on max plus simulator I got many "glitches". is there
    some way to elimante it?? is very important for me to eliminate it,
    ´cause I use the output sgnals as input signals of other component.

    any suggestions
    thanks in advance..
    JLuis

    this is my code.

    -- Opcode Decoder March 19th, 2004 José Luis
    Fernández Jiménez

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.all;


    ENTITY opdecoder IS

    PORT( decdataop : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
    NOPgp, ADDgp, SUBgp, ADIgp, ANDgp, ORgp, NOTgp, NEGgp, SHLgp,
    SHRgp, LDRgp,
    STRgp, LDIgp, MOVgp, LDXgp, STXgp, SSPgp, PSHgp, POPgp, JMPgp,
    JPLUSgp, JPZgp,
    JNEGgp, JNZgp, JZEgp, JSUBgp, RETgp: OUT std_logic
    );

    END opdecoder;

    ARCHITECTURE archopdecoder OF opdecoder IS
    SIGNAL temp_op : STD_LOGIC_VECTOR(31 DOWNTO 0);

    BEGIN
    PROCESS (decdataop)
    BEGIN

    CASE decdataop IS
    WHEN "00000" =>
    temp_op <= "00000000000000000000000000000001"; --
    NOPgp 0
    WHEN "00001" =>
    temp_op <= "00000000000000000000000000000010"; --
    ADDgp 1
    WHEN "00010" =>
    temp_op <= "00000000000000000000000000000100"; --
    SUBgp 2
    WHEN "00011" =>
    temp_op <= "00000000000000000000000000001000"; --
    ADIgp 3
    WHEN "00100" =>
    temp_op <= "00000000000000000000000000010000"; --
    ANDgp 4
    WHEN "00101" =>
    temp_op <= "00000000000000000000000000100000"; -- ORgp
    5
    WHEN "00110" =>
    temp_op <= "00000000000000000000000001000000"; --
    NOTgp 6
    WHEN "00111" =>
    temp_op <= "00000000000000000000000010000000"; --
    NEGgp 7
    WHEN "01000" =>
    temp_op <= "00000000000000000000000100000000"; --
    SHLgp 8
    WHEN "01001" =>
    temp_op <= "00000000000000000000001000000000"; --
    SHRgp 9
    WHEN "01010" =>
    temp_op <= "00000000000000000000010000000000"; --
    LDRgp 10
    WHEN "01011" =>
    temp_op <= "00000000000000000000100000000000"; --
    STRgp 11
    WHEN "01100" =>
    temp_op <= "00000000000000000001000000000000"; --
    LDIgp 12
    WHEN "01101" =>
    temp_op <= "00000000000000000010000000000000"; --
    MOVgp 13
    WHEN "01110" =>
    temp_op <= "00000000000000000100000000000000"; --
    LDXgp 14
    WHEN "01111" =>
    temp_op <= "00000000000000001000000000000000"; --
    STXgp 15
    WHEN "10000" =>
    temp_op <= "00000000000000010000000000000000"; --
    SSPgp 16
    WHEN "10001" =>
    temp_op <= "00000000000000100000000000000000"; --
    PSHgp 17
    WHEN "10010" =>
    temp_op <= "00000000000001000000000000000000"; --
    POPgp 18
    WHEN "10011" =>
    temp_op <= "00000000000010000000000000000000"; --
    JMPgp 19
    WHEN "10100" =>
    temp_op <= "00000000000100000000000000000000"; --
    JPLUSgp 20
    WHEN "10101" =>
    temp_op <= "00000000001000000000000000000000"; --
    JPZgp 21
    WHEN "10110" =>
    temp_op <= "00000000010000000000000000000000"; --
    JNEGgp 22
    WHEN "10111" =>
    temp_op <= "00000000100000000000000000000000"; --
    JNZgp 23
    WHEN "11000" =>
    temp_op <= "00000001000000000000000000000000"; --
    JZEgp 24
    WHEN "11001" =>
    temp_op <= "00000010000000000000000000000000"; --
    JSUBgp 25
    WHEN "11010" =>
    temp_op <= "00000100000000000000000000000000"; --
    RETgp 26
    WHEN OTHERS => NULL;
    -- temp_op <= "00000000000000000000000000000000";
    END CASE;

    END PROCESS;

    NOPgp <= temp_op(0);
    ADDgp <= temp_op(1);
    SUBgp <= temp_op(2);
    ADIgp <= temp_op(3);
    ANDgp <= temp_op(4);
    ORgp <= temp_op(5);
    NOTgp <= temp_op(6);
    NEGgp <= temp_op(7);
    SHLgp <= temp_op(8);
    SHRgp <= temp_op(9);
    LDRgp <= temp_op(10);
    STRgp <= temp_op(11);
    LDIgp <= temp_op(12);
    MOVgp <= temp_op(13);
    LDXgp <= temp_op(14);
    STXgp <= temp_op(15);
    SSPgp <= temp_op(16);
    PSHgp <= temp_op(17);
    POPgp <= temp_op(18);
    JMPgp <= temp_op(19);
    JPLUSgp <= temp_op(20);
    JPZgp <= temp_op(21);
    JNEGgp <= temp_op(22);
    JNZgp <= temp_op(23);
    JZEgp <= temp_op(24);
    JSUBgp <= temp_op(25);
    RETgp <= temp_op(26);

    END archopdecoder;
     
    Jluis, May 5, 2004
    #1
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  2. Jluis

    Jim Wu Guest


    > Hi everyone!!!! I program a big decoder, so the compilation is ok, but
    > when I simulated on max plus simulator I got many "glitches". is there
    > some way to elimante it?? is very important for me to eliminate it,
    > ´cause I use the output sgnals as input signals of other component.
    >


    Register the output with a clock.

    HTH,
    Jim

    http://www.geocities.com/jimwu88/chips
     
    Jim Wu, May 5, 2004
    #2
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  3. "Jim Wu" <> wrote in message
    news:_eZlc.24999$...
    >
    > > Hi everyone!!!! I program a big decoder, so the compilation is ok,

    but
    > > when I simulated on max plus simulator I got many "glitches". is

    there
    > > some way to elimante it?? is very important for me to eliminate it,
    > > ´cause I use the output sgnals as input signals of other component.
    > >

    >
    > Register the output with a clock.


    Yes, I think that is the only way to eliminate the glitches. A
    combinational circuit like this is inherently glitchy.
     
    Charles Bailey, May 8, 2004
    #3
  4. (Jluis) wrote in message news:<>...
    > Hi everyone!!!! I program a big decoder, so the compilation is ok, but
    > when I simulated on max plus simulator I got many "glitches". is there
    > some way to elimante it?? is very important for me to eliminate it,
    > ´cause I use the output sgnals as input signals of other component.


    You have two possibilities:
    1. register the output
    2. break your code down to structural code and use technics [1] to
    eliminate glitches in digital cirquits.

    bye Thomas

    [1] In principle all you have to do is to ensure, that there are no
    two inputs in a gate that change at the same time while the output of
    the gate would change if only one of the two inputs would change but
    not if both inputs change their value.
     
    Thomas Stanka, May 10, 2004
    #4
  5. Jluis

    DoesntMatter Guest

    Is this a question on electronics design ? Do you know how you are going
    to handle in reality ? Then just model it afer that ...

    Or is the question something different ?

    Jos De Laender

    Jluis wrote:
    > Hi everyone!!!! I program a big decoder, so the compilation is ok, but
    > when I simulated on max plus simulator I got many "glitches". is there
    > some way to elimante it?? is very important for me to eliminate it,
    > ´cause I use the output sgnals as input signals of other component.
    >
    > any suggestions
    > thanks in advance..
    > JLuis
    >
    > this is my code.
    >
    > -- Opcode Decoder March 19th, 2004 José Luis
    > Fernández Jiménez
    >
    > LIBRARY IEEE;
    > USE IEEE.STD_LOGIC_1164.all;
    >
    >
    > ENTITY opdecoder IS
    >
    > PORT( decdataop : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
    > NOPgp, ADDgp, SUBgp, ADIgp, ANDgp, ORgp, NOTgp, NEGgp, SHLgp,
    > SHRgp, LDRgp,
    > STRgp, LDIgp, MOVgp, LDXgp, STXgp, SSPgp, PSHgp, POPgp, JMPgp,
    > JPLUSgp, JPZgp,
    > JNEGgp, JNZgp, JZEgp, JSUBgp, RETgp: OUT std_logic
    > );
    >
    > END opdecoder;
    >
    > ARCHITECTURE archopdecoder OF opdecoder IS
    > SIGNAL temp_op : STD_LOGIC_VECTOR(31 DOWNTO 0);
    >
    > BEGIN
    > PROCESS (decdataop)
    > BEGIN
    >
    > CASE decdataop IS
    > WHEN "00000" =>
    > temp_op <= "00000000000000000000000000000001"; --
    > NOPgp 0
    > WHEN "00001" =>
    > temp_op <= "00000000000000000000000000000010"; --
    > ADDgp 1
    > WHEN "00010" =>
    > temp_op <= "00000000000000000000000000000100"; --
    > SUBgp 2
    > WHEN "00011" =>
    > temp_op <= "00000000000000000000000000001000"; --
    > ADIgp 3
    > WHEN "00100" =>
    > temp_op <= "00000000000000000000000000010000"; --
    > ANDgp 4
    > WHEN "00101" =>
    > temp_op <= "00000000000000000000000000100000"; -- ORgp
    > 5
    > WHEN "00110" =>
    > temp_op <= "00000000000000000000000001000000"; --
    > NOTgp 6
    > WHEN "00111" =>
    > temp_op <= "00000000000000000000000010000000"; --
    > NEGgp 7
    > WHEN "01000" =>
    > temp_op <= "00000000000000000000000100000000"; --
    > SHLgp 8
    > WHEN "01001" =>
    > temp_op <= "00000000000000000000001000000000"; --
    > SHRgp 9
    > WHEN "01010" =>
    > temp_op <= "00000000000000000000010000000000"; --
    > LDRgp 10
    > WHEN "01011" =>
    > temp_op <= "00000000000000000000100000000000"; --
    > STRgp 11
    > WHEN "01100" =>
    > temp_op <= "00000000000000000001000000000000"; --
    > LDIgp 12
    > WHEN "01101" =>
    > temp_op <= "00000000000000000010000000000000"; --
    > MOVgp 13
    > WHEN "01110" =>
    > temp_op <= "00000000000000000100000000000000"; --
    > LDXgp 14
    > WHEN "01111" =>
    > temp_op <= "00000000000000001000000000000000"; --
    > STXgp 15
    > WHEN "10000" =>
    > temp_op <= "00000000000000010000000000000000"; --
    > SSPgp 16
    > WHEN "10001" =>
    > temp_op <= "00000000000000100000000000000000"; --
    > PSHgp 17
    > WHEN "10010" =>
    > temp_op <= "00000000000001000000000000000000"; --
    > POPgp 18
    > WHEN "10011" =>
    > temp_op <= "00000000000010000000000000000000"; --
    > JMPgp 19
    > WHEN "10100" =>
    > temp_op <= "00000000000100000000000000000000"; --
    > JPLUSgp 20
    > WHEN "10101" =>
    > temp_op <= "00000000001000000000000000000000"; --
    > JPZgp 21
    > WHEN "10110" =>
    > temp_op <= "00000000010000000000000000000000"; --
    > JNEGgp 22
    > WHEN "10111" =>
    > temp_op <= "00000000100000000000000000000000"; --
    > JNZgp 23
    > WHEN "11000" =>
    > temp_op <= "00000001000000000000000000000000"; --
    > JZEgp 24
    > WHEN "11001" =>
    > temp_op <= "00000010000000000000000000000000"; --
    > JSUBgp 25
    > WHEN "11010" =>
    > temp_op <= "00000100000000000000000000000000"; --
    > RETgp 26
    > WHEN OTHERS => NULL;
    > -- temp_op <= "00000000000000000000000000000000";
    > END CASE;
    >
    > END PROCESS;
    >
    > NOPgp <= temp_op(0);
    > ADDgp <= temp_op(1);
    > SUBgp <= temp_op(2);
    > ADIgp <= temp_op(3);
    > ANDgp <= temp_op(4);
    > ORgp <= temp_op(5);
    > NOTgp <= temp_op(6);
    > NEGgp <= temp_op(7);
    > SHLgp <= temp_op(8);
    > SHRgp <= temp_op(9);
    > LDRgp <= temp_op(10);
    > STRgp <= temp_op(11);
    > LDIgp <= temp_op(12);
    > MOVgp <= temp_op(13);
    > LDXgp <= temp_op(14);
    > STXgp <= temp_op(15);
    > SSPgp <= temp_op(16);
    > PSHgp <= temp_op(17);
    > POPgp <= temp_op(18);
    > JMPgp <= temp_op(19);
    > JPLUSgp <= temp_op(20);
    > JPZgp <= temp_op(21);
    > JNEGgp <= temp_op(22);
    > JNZgp <= temp_op(23);
    > JZEgp <= temp_op(24);
    > JSUBgp <= temp_op(25);
    > RETgp <= temp_op(26);
    >
    > END archopdecoder;
     
    DoesntMatter, May 10, 2004
    #5
  6. Jluis

    Ray Andraka Guest

    Not the only way, but perhaps the easiest way.

    If the circuit must be combinatorial, you can design the combinatorial
    circuit with cover terms to avoid the hazards that result in glitches.
    Refer to a basic logic book such as Morris Mano for a detailed discussion on
    cover terms and static hazards. The trick then, is to keep your synthesis
    tool from optimizing out the cover terms that prevent the static hazards.

    Charles Bailey wrote:

    >
    > > Register the output with a clock.

    >
    > Yes, I think that is the only way to eliminate the glitches. A
    > combinational circuit like this is inherently glitchy.


    --
    --Ray Andraka, P.E.
    President, the Andraka Consulting Group, Inc.
    401/884-7930 Fax 401/884-7950
    email
    http://www.andraka.com

    "They that give up essential liberty to obtain a little
    temporary safety deserve neither liberty nor safety."
    -Benjamin Franklin, 1759
     
    Ray Andraka, May 12, 2004
    #6
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