How can I have multiple drivers of one inout port?

Discussion in 'VHDL' started by cruzin, Jan 21, 2004.

  1. cruzin

    cruzin Guest

    Hi,

    I am trying to connect the bidirectional ports of two components to
    one bidirectional set of pins on my FPGA. Is it possible to do this in
    VHDL? The following example does not appear to read the bidir port:

    entity whatever
    port (
    signal choice : in std_logic;
    signal my_bidir : inout std_logic
    );
    end;

    architecture rtl of whatever is

    signal x0_bidir,
    x1_bidir : std_logic;

    begin

    xInstOne : x
    port map (
    my_bidir_port => x0_bidir );

    xInstTwo: x
    port map (
    my_bidir_port => x1_bidir );

    my_bidir <= x0_bidir when choice='0' else x1_bidir;

    end;

    ==========================

    Is there any way to modify this to make it work, or am I stuck with
    exporting both input and output ports from the components and muxing
    them at the top level?
     
    cruzin, Jan 21, 2004
    #1
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  2. f'up comp.lang.vhdl set

    cruzin wrote:

    > I am trying to connect the bidirectional ports of two components to
    > one bidirectional set of pins on my FPGA. Is it possible to do this in
    > VHDL?


    Take tri-state drivers

    process(enable,some_signal)
    begin
    if (enable='1') then
    target_signal<=some_signal;
    else target_signal<=(others=>'Z');
    end if;
    end process;

    target_signal has to be of std_logic(_vector), because it has to be
    resoled (multiple drivers).

    Take care, that *only one* of these tri-state-drivers are activated at a
    time.

    Take care, that everytime *at least one* driver is active (otherwise
    target_signal would float).


    Think about providing these enable-signals to the tri-state-drivers.
    E.g. if you have several memory blocks, the address may decide, which
    block is allowed to drive target_signal -> the enable-signals can be
    generated thorugh combinational logic out of the address.


    Ralf
     
    Ralf Hildebrandt, Jan 22, 2004
    #2
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  3. cruzin

    PO Laprise Guest

    Ralf Hildebrandt wrote:
    > Take care, that everytime *at least one* driver is active (otherwise
    > target_signal would float).


    Of course, having a floating signal doesn't matter as long as you don't
    try to read it. To be more precise, you should take care that one and
    only one driver is active when someone needs to read the bus.

    --
    Pierre-Olivier

    -- to email me directly, remove all _N0SP4M_ from my address --
     
    PO Laprise, Jan 23, 2004
    #3
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