How do I fix this conversion problem?

Discussion in 'VHDL' started by G Iveco, Sep 8, 2007.

  1. G Iveco

    G Iveco Guest

    I am studying VHDL with this simple module, and the conversion between
    std_logic_vector and
    unsigned/signed is really troublesome!

    I need all IOs to be in std_logic/vector, but inside some computations can
    take on other
    standards.

    Thank you in advance!



    # ** Error: ../RTL/channel_awgn.vhd(38): No feasible entries for subprogram
    "to_bitvector".
    # ** Error: ../RTL/channel_awgn.vhd(53): VHDL Compiler exiting
    # C:/Programs/Modeltech_xe_starter/win32xoem/vcom failed.





    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use IEEE.math_real.uniform;

    entity channel_awgn is
    port (
    clk_in : in std_logic;
    rstn_in : in std_logic;

    conv_in : in std_logic_vector(1 downto 0);
    conv_en_in : in std_logic;
    snr_in : in std_logic_vector(7 downto 0);

    rx_data_out : out std_logic_vector(7 downto 0);
    rx_en_out : out std_logic
    );
    end channel_awgn;

    architecture channel of channel_awgn is

    begin

    process(clk_in, rstn_in)
    variable seed1, seed2 : positive := 1;
    variable a_real : real;
    variable noise : integer;
    variable tmp_us: unsigned(7 downto 0);
    begin
    if rstn_in = '0' then
    rx_data_out <= (others=>'0');
    elsif rising_edge(clk_in) then
    uniform(seed1, seed2, a_real);
    noise := natural(a_real * real(2**8) - 0.5);
    if (conv_en_in = '1') then
    tmp_us := unsigned('0' & conv_in & b"01000") + to_unsigned(noise, 8);
    rx_data_out <= to_StdLogicVector(to_bitvector(tmp_us)); <========
    Here is line 38.
    end if;
    end if;
    end process;

    end channel;
     
    G Iveco, Sep 8, 2007
    #1
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  2. G Iveco

    Alain Guest

    Hi,

    Simply :

    rx_data_out <= Std_Logic_Vector(tmp_us);

    Best regards.
     
    Alain, Sep 8, 2007
    #2
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