How do i make a race timerA in VHDL?

Discussion in 'VHDL' started by trickae, May 16, 2007.

  1. trickae

    trickae

    Joined:
    May 16, 2007
    Messages:
    1
    Here's the timer template I'm given - I'm not sure how to implement the finite state machine for the main part of the code. Any help would be highly appreciated

    Code (Text):

    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;

    entity timer is
        port (
        clk_in: in STD_LOGIC;
            reset: in STD_LOGIC;
            push_button: in STD_LOGIC;
            current_state: out STD_LOGIC_VECTOR (1 downto 0);
            digit0: out STD_LOGIC_VECTOR (3 downto 0);
            digit1: out STD_LOGIC_VECTOR (3 downto 0);
            digit2: out STD_LOGIC_VECTOR (3 downto 0);
            digit3: out STD_LOGIC_VECTOR (3 downto 0)
        );
    end timer;

    architecture timer_arch of timer is

    signal count_enable0: STD_LOGIC;    --enable signal for 1st counter
    signal count_enable1: STD_LOGIC;    --enable signal for 2nd counter
    signal count_out0: STD_LOGIC;       --countrol output of 1st counter
    signal count_out1: STD_LOGIC;       --countrol output of 2nd counter
    signal count_out2: STD_LOGIC;       --countrol output of 3rd counter
    signal count_out3: STD_LOGIC;       --countrol output of 4th counter

    signal next_state: STD_LOGIC_VECTOR (1 downto 0);   --next state variables
    signal present_state: STD_LOGIC_VECTOR (1 downto 0);    --present state variable

    signal clk_out: STD_LOGIC;              --divided clock output
    signal clk_divider: STD_LOGIC_VECTOR(3 downto 0);   --clock divider counter

    CONSTANT A: STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";       -- state A
    CONSTANT B: STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";       -- state B
    CONSTANT C: STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";       -- state C
    CONSTANT D: STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";       -- state D


    ----------------------------------------
    --BCD counter component - DO NOT MODIFY
    ----------------------------------------

    component bcd_counter
        port (
                reset: in STD_LOGIC;
                clk: in STD_LOGIC;
                count_enable: in STD_LOGIC;
                carry_out: out STD_LOGIC;
                digit_out: out STD_LOGIC_VECTOR (3 downto 0)
            );
    end component;

    begin


        -------------------------
        --FSM flip flop process,
        -------------------------
        process(push_button, reset)
        begin

            --Reset the FSM to state A if the reset
            --signal is low.
            if reset = '0' then
                present_state <= A;
           
            --The FSM state changes on the rising edge of the push button.
            --The physical push button has been compensated for switch bouncing.   
            elsif push_button'EVENT and push_button = '1' then
           
                present_state <= next_state;
            end if;
        end process;

        ----------------------------------------   
        --FSM next state logic process
        ----------------------------------------
        process(present_state)
        begin
            case present_state is
               
                -----------------------------------
                --ENTER YOUR NEXT STATE LOGIC HERE   
                --Design the controller as an FSM.
                --Choose the type of FSM (Moore or Mealy)
                --to suit the problem, but remember that
                --Moore is always easier to design with reliably.
                -----------------------------------        
           
            end case;
        end process;

        ---------------------------------------------------------------
        --Enter Your connecting logic for the FSM to counter interface.
        ---------------------------------------------------------------

               
            --clock divder process is used to lower
            --the clock speed by using a counter.
            process(clk_in, reset)
            begin

            -------------------------------------
            --ENTER YOUR CLOCK DIVIDER LOGIC HERE
            --Decide what clock frequency you need in your design.
            --Use the clock signal from the clock generator supplied
            --in the timer design template file to obtain appropriate clock for your design.
            -------------------------------------                  
               
            end process;
           
        --Link clock divider output to the clock divider counter.
            clk_out <= clk_divider(3);
       
     
    end timer_arch;
     
     
    trickae, May 16, 2007
    #1
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