erratum: for "a","b", or "d" : read "b" or "d"
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Ignoring the impacts of optimization (deleting unused outputs, and
everything that only drives them), there are some problems with the
code.
Specifically, z is not always assigned a value, which would result in
a latch were z not to be optimized out in the first place, whether z
were a variable or signal. Latches are an inherent risk in
combinatorial processes. The same situation in a clocked process
merely results in a clock disable on a register, and/or (with
variables) a mux between the input and output of the register, where z
might be referenced subsequently. Interestingly, the output of the
implied clock-disabling feedback mux, before the register input, is
exactly what is needed for successive references to the conditionally
assigned variable.
Because y is overwritten in each loop iteration, the whole loop
collapses to just the last iteration of the loop, ignoring the
previous iterations. This has nothing to do with signals vs variables.
The typical impact on truly iterative loops of variables vs signals is
that since signals do not get updated until the process suspends,
there is no real iteration upon signals inside a loop (assuming there
are no wait statements in the loop). Since variables do update
immediately, iteration upon the variable is possible, it is just not
demonstrated in the example. Just remember that all loops not
containing wait statements are simply unrolled during synthesis. Not
all synthesis tools can handle loops with wait statements (i.e.
waiting on the next clock edge), but that is probably beyond the
intended scope of discussion.
Because sensitivity lists are ignored in synthesis, the synthesis of x
is unrelated to variable vs signal behavior. Were x a signal, the
synthesis result would assume x were also in the sensitivity list, and
the resulting behavior would be identical to that of a variable x. In
simulation, if x were a signal, and included in the process
sensitivity list, it would cause the process to immediately run again
with the updated value of x, thus allowing propagation to the
subsequent references to x within the process.
So, in effect, most of the behavior of the code, even ignoring the
effects of optimization during synthesis, really does not have much to
do with variable vs signal behavior.
Andy