How does ASIC compiler compile for if..else..

Discussion in 'VHDL' started by Weng Tianxiang, Dec 8, 2004.

  1. Hi,
    if(x1 = '1') then -- (1)
    R <= y1;
    elsif(x2 = '1') then
    R <= y1;
    ....
    end if;
    The above equations are common in VHDL. For a FPGA chip, VHDL compiler
    will generate the following equation (2) for (1):

    R <= (x1 and y1) or (not x1 and x2 and y2) + ...; --(2)

    And based on FPGA structure, compiler will generate intermediate 4
    input LUTs to replace the above equation in its final equation.

    I would like to know if equation (1) is compiled into equation (2) for
    an ASIC chip by all ASIC VHDL compilers, especially from several
    predominate VHDL ASIC compiler companies?

    Or any other methods?
    The above discussion doesn't include all optimization of (2).

    Weng
     
    Weng Tianxiang, Dec 8, 2004
    #1
    1. Advertising

  2. Weng Tianxiang

    rickman Guest

    Weng Tianxiang wrote:
    >
    > Hi,
    > if(x1 = '1') then -- (1)
    > R <= y1;
    > elsif(x2 = '1') then
    > R <= y1;
    > ...
    > end if;
    > The above equations are common in VHDL. For a FPGA chip, VHDL compiler
    > will generate the following equation (2) for (1):
    >
    > R <= (x1 and y1) or (not x1 and x2 and y2) + ...; --(2)
    >
    > And based on FPGA structure, compiler will generate intermediate 4
    > input LUTs to replace the above equation in its final equation.
    >
    > I would like to know if equation (1) is compiled into equation (2) for
    > an ASIC chip by all ASIC VHDL compilers, especially from several
    > predominate VHDL ASIC compiler companies?
    >
    > Or any other methods?
    > The above discussion doesn't include all optimization of (2).


    What you call equation 1 is not an equation, it is an HDL description.
    It will be translated into equation 2 when compiled. Equation 2 may be
    optimized into anything equivalent for implementation as the compiler
    sees fit.

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Dec 8, 2004
    #2
    1. Advertising

  3. Weng Tianxiang

    Tom Verbeure Guest

    Yes, an ASIC synthesizer will do the same thing as an FPGA synthesizer:
    it will create logic that matches your hdl description. If he has
    additional information that can legally allow him to optimize, it may
    do so, but given only the information that you have given, it should do
    exactly what you requested. (But of course, you already knew that. :)
    )

    Tom
     
    Tom Verbeure, Dec 9, 2004
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Nikolaos Kefalas
    Replies:
    2
    Views:
    941
  2. Replies:
    25
    Views:
    674
    MonkeeSage
    Oct 1, 2006
  3. Nagaraj
    Replies:
    1
    Views:
    876
    Lionel B
    Mar 1, 2007
  4. kj
    Replies:
    15
    Views:
    560
    Lawrence D'Oliveiro
    May 23, 2009
  5. A
    Replies:
    8
    Views:
    810
    James Kanze
    Aug 28, 2010
Loading...

Share This Page