How dofor using generate or loop for this process ?

Discussion in 'VHDL' started by Olivier Dir, Apr 1, 2014.

  1. Olivier Dir

    Olivier Dir Guest

    Hi all,
    for this code I would like write this code with loop or generate.
    I don't know if it's possible.



    pSelFifo : process(Clk, SRst)
    begin
    if SRst = '1' then
    SelFifo <= (others=>'0');
    elsif Clk'event and Clk='1' then
    if DataAvlble(1) = '1' then
    SelFifo <= "000001"
    elsif DataAvlble(2) = '1' then
    SelFifo <= "000010"
    elsif DataAvlble(3) = '1' then
    SelFifo <= "000100"
    elsif DataAvlble(4) = '1' then
    SelFifo <= "001000"
    elsif DataAvlble(5) = '1' then
    SelFifo <= "010000"
    elsif DataAvlble(6) = '1' then
    SelFifo <= "100000"
    else
    SelFifo <= (others=>'0');
    end if;

    end if;
    end process;

    thank for your help.

    Olive
     
    Olivier Dir, Apr 1, 2014
    #1
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  2. Olivier Dir

    Olivier Dir Guest

    Le mardi 1 avril 2014 13:25:02 UTC+2, Brian Drummond a écrit :
    > On Tue, 01 Apr 2014 03:04:29 -0700, Olivier Dir wrote:
    >
    >
    >
    > > Hi all,

    >
    > > for this code I would like write this code with loop or generate.

    >
    > > I don't know if it's possible.

    >
    > >

    >
    > >

    >
    > >

    >
    > > pSelFifo : process(Clk, SRst)

    >
    > > begin

    >
    > > if SRst = '1' then

    >
    > > SelFifo <= (others=>'0');

    >
    > > elsif Clk'event and Clk='1' then

    >
    > > if DataAvlble(1) = '1' then

    >
    > > SelFifo <= "000001"

    >
    > > elsif DataAvlble(2) = '1' then

    >
    > > SelFifo <= "000010"

    >
    > ...
    >
    >
    >
    > > thank for your help.

    >
    > >

    >
    > > Olive

    >
    >
    >
    > pSelFifo : process(Clk, SRst)
    >
    > begin
    >
    > if SRst = '1' then
    >
    > SelFifo <= (others=>'0');
    >
    > elsif rising_edge(Clk) then
    >
    > SelFifo <= (others=>'0');
    >
    > for i in DataAvlble'low to DataAvlble'high loop
    >
    > if DataAvlble(i) = '1' then
    >
    > SelFifo(i) <= '1';
    >
    > exit; -- prevent multiple bit set, as in original
    >
    > end if;
    >
    > end loop;
    >
    > end if;
    >
    > end process;


    Thank you.
     
    Olivier Dir, Apr 2, 2014
    #2
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  3. Olivier Dir

    Andy Guest

    It is not clear from the example what is the index range on SelFifo, and ifthat range matches the range of DataAvlble. We do know that Selfifo has 6 bits. DataAvlble has at least 6 bits, indexed between 6 and 1 inclusive, but we do not know DataAvlble's index range direction.

    The loop would only work if SelFifo'range is 6 downto 1.

    The following would work if the index diretion of both DataAvlble and SelFifo is "downto", given the correct value for DaOffset:

    pSelFifo : process(Clk, SRst)
    constant DaOffset : integer := 1;
    begin
    if SRst = '1' then
    SelFifo <= (others=>'0');
    elsif rising_edge(Clk) then
    SelFifo <= (others=>'0');
    for i in SelFifo'reverse_range loop -- right to left in SelFifo
    if DataAvlble(i + DaOffset) = '1' then
    SelFifo(i) <= '1';
    exit; -- prevent multiple bit set, as in original
    end if;
    end loop;
    end if;
    end process;

    The sum (i + DaOffset) becomes a constant when synthesis unrolls the loop.

    Andy
     
    Andy, Apr 4, 2014
    #3
  4. Olivier Dir

    Daniel Kho Guest

    On Saturday, 5 April 2014 01:07:00 UTC+8, Andy wrote:
    > It is not clear from the example what is the index range on SelFifo, and if that range matches the range of DataAvlble. We do know that Selfifo has 6 bits. DataAvlble has at least 6 bits, indexed between 6 and 1 inclusive, but we do not know DataAvlble's index range direction.
    >
    >
    >
    > The loop would only work if SelFifo'range is 6 downto 1.
    >
    >
    >
    > The following would work if the index diretion of both DataAvlble and SelFifo is "downto", given the correct value for DaOffset:
    >
    >
    >
    > pSelFifo : process(Clk, SRst)
    >
    > constant DaOffset : integer := 1;
    >
    > begin
    >
    > if SRst = '1' then
    >
    > SelFifo <= (others=>'0');
    >
    > elsif rising_edge(Clk) then
    >
    > SelFifo <= (others=>'0');
    >
    > for i in SelFifo'reverse_range loop -- right to left in SelFifo
    >
    > if DataAvlble(i + DaOffset) = '1' then
    >
    > SelFifo(i) <= '1';
    >
    > exit; -- prevent multiple bit set, as in original
    >
    > end if;
    >
    > end loop;
    >
    > end if;
    >
    > end process;
    >
    >
    >
    > The sum (i + DaOffset) becomes a constant when synthesis unrolls the loop..
    >
    >
    >
    > Andy



    Something like this might just work (not tested):

    signal n: positive;
    ....
    pSelFifo : process(Clk, SRst) begin
    if SRst = '1' then
    SelFifo <= (others=>'0');
    elsif Clk'event and Clk='1' then
    if n>6 then SelFifo <= (others=>'0');
    else
    if DataAvlble(n) then SelFifo <= to_unsigned(2**(n-1),6); end if;
    end if;
    end if;
    end process;

    Not sure though if this will synthesise. Probably not, since the expression(2**(n-1)) is not a constant. However, this can be replaced by a shift-left operation for synthesis. We could try that as well.

    -daniel
     
    Daniel Kho, Apr 8, 2014
    #4
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