How to access individual bits of std_logic_vector

[Daku]

Could some VHDL guru please help ? I am using the Alliance 5.0 tool. I
have:

ARCHITECTURE dataflow_view OF ram IS
SUBTYPE INDX IS std_logic_vector(0 to 31);
SIGNAL index : INDX;
-- Some other declarations
Now, inside a process, I wish to examine the content of each location
in index - if it is '0'
do something as in:

BEGIN

RAM_0 : PROCESS( WEB )
VARIABLE cnt : INTEGER RANGE 0 TO 31;

BEGIN
IF (WEB='1' AND WEB'EVENT )
THEN IF (REB='0') THEN
IF (index(0) = '0') THEN
cnt := 0;
END IF;
--memory( CONV_INTEGER( A ) ) <= INN;
END IF;
END IF;
END PROCESS RAM_0;

I am getting an error message as:
--> Run VHDL Compiler
--> Compile file ram
parse 118 ERROR size of atom index_idx_0 should be static

Any hints, suggestions would be of immense help. Thanks in advance for
your help.

 

[Tricky]

Could some VHDL guru please help ? I am using the Alliance 5.0 tool. I
have:

ARCHITECTURE dataflow_view OF ram IS
    SUBTYPE INDX IS std_logic_vector(0 to 31);
    SIGNAL index : INDX;
-- Some other declarations
Now, inside a process, I wish to examine the content of each location
in index - if it is '0'
do something as in:

BEGIN

    RAM_0 : PROCESS( WEB )
    VARIABLE cnt : INTEGER RANGE 0 TO 31;

    BEGIN
    IF (WEB='1' AND WEB'EVENT )
     THEN IF (REB='0') THEN
         IF (index(0) = '0') THEN
           cnt := 0;
         END IF;
         --memory( CONV_INTEGER( A ) ) <= INN;
         END IF;
    END IF;
   END PROCESS RAM_0;

I am getting an error message as:
        --> Run VHDL Compiler
        --> Compile file ram
parse    118 ERROR size of atom index_idx_0 should be static

Any hints, suggestions would be of immense help. Thanks in advance for
your help.

You dont make much sense, as there isnt anything wrong you the code
you've posted. Are you trying to find the first index of a
std_logic_vector that is '0'? or every index? What do you want to do
when you've discovered one bit is '0'?

 

[Daku]

I want to iterate over each element of
std_logic_vector, and depending on whether it is
'1' or '0', do something else.

 

[KJ]

I want to iterate over each element of
std_logic_vector, and depending on whether it is
'1' or '0', do something else.

You would use a for loop to iterate over the range of a vector and an
if statement to do conditional logic. An example below

process(Clock)
begin
if rising_edge(Clock) then
for Index in My_Vec'range loop
if My_Vec(Index) = '1' then
-- Do something
else
-- Do something else
end if;
end loop;
end if;
end process;

Kevin Jennings

 

[Daku]

I fully agree/understand and have tried out what you have said below,
but I am getting an error
message that does not make much sense to me. I
am using the Alliance 5.0 toolset.
I have :

ENTITY ram IS
port ( A : in std_logic_vector(0 to 31);
CEB : in std_logic;
WEB : in std_logic;
REB : in std_logic;
INN : in std_logic_vector(0 to 31);
OUTT : out std_logic_vector(0 to 31)
);
END ram;

ARCHITECTURE dataflow_view OF ram IS
SUBTYPE INDX IS std_logic_vector(0 to 31);
SIGNAL index : INDX;

--Some other declarations

BEGIN

RAM_0 : PROCESS( WEB )
VARIABLE cnt : INTEGER RANGE 0 TO 31;

BEGIN
IF (WEB='1' AND WEB'EVENT )
THEN IF (REB='0') THEN
IF (index(0) = '0') THEN
cnt := 0;
END IF;
memory( CONV_INTEGER( A ) ) <= INN;
END IF;
END IF;
END PROCESS RAM_0;

-- Some other processes
The compile time error message is:

--> Run VHDL Compiler
--> Compile file ram
parse 118 ERROR size of atom index_idx_0 should be static

Looks like it does not like : IF (index(0) = '0')

Could someone please point out what exactly is the
problem ?

 

[StuartHobday]

Index has been declared as an internal signal but where is it actually being assigned a value?

Here is an example using a snippet from your code:

index<= A;

IndexTest : PROCESS( WEB )
BEGIN
***IF (WEB='1' AND WEB'EVENT ) THEN
******IF (REB = '0') THEN
*********IF (index(0) = '0') THEN
************OUTT<= INN;
*********END IF;
******END IF;
***END IF;
END PROCESS;

Hopefully this will help!

 

[Daku]

I thank each one of you for your feedback. The really funny thing
is that if I have :
ARCHITECTURE dataflow_view OF ram IS
SIGNAL index : std_logic_vector (0 to 31);

Instead of :
ARCHITECTURE dataflow_view OF ram IS
SUBTYPE INDX IS std_logic_vector(0 to 31);
SIGNAL index : INDX;

Then the following compiles without a murmur of protest:
RAM_0 : PROCESS( WEB )
VARIABLE cnt : INTEGER RANGE 0 TO 31;

BEGIN
IF WEB='1' AND WEB'EVENT
THEN IF REB='0' THEN
FOR I IN index'RANGE LOOP
IF index(I) = '0' THEN
cnt := I;
EXIT;
END IF;
END LOOP;
memory( CONV_INTEGER( A ) ) <= INN;

So right now I am hunting for a good VHDL simulator/verifier.
Thank you all.