How to access individual bits of std_logic_vector

Discussion in 'VHDL' started by Daku, Nov 19, 2009.

  1. Daku

    Daku Guest

    Could some VHDL guru please help ? I am using the Alliance 5.0 tool. I
    have:

    ARCHITECTURE dataflow_view OF ram IS
    SUBTYPE INDX IS std_logic_vector(0 to 31);
    SIGNAL index : INDX;
    -- Some other declarations
    Now, inside a process, I wish to examine the content of each location
    in index - if it is '0'
    do something as in:

    BEGIN

    RAM_0 : PROCESS( WEB )
    VARIABLE cnt : INTEGER RANGE 0 TO 31;

    BEGIN
    IF (WEB='1' AND WEB'EVENT )
    THEN IF (REB='0') THEN
    IF (index(0) = '0') THEN
    cnt := 0;
    END IF;
    --memory( CONV_INTEGER( A ) ) <= INN;
    END IF;
    END IF;
    END PROCESS RAM_0;

    I am getting an error message as:
    --> Run VHDL Compiler
    --> Compile file ram
    parse 118 ERROR size of atom index_idx_0 should be static

    Any hints, suggestions would be of immense help. Thanks in advance for
    your help.
     
    Daku, Nov 19, 2009
    #1
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  2. Daku

    Tricky Guest

    On 19 Nov, 04:28, Daku <> wrote:
    > Could some VHDL guru please help ? I am using the Alliance 5.0 tool. I
    > have:
    >
    > ARCHITECTURE dataflow_view OF ram IS
    >     SUBTYPE INDX IS std_logic_vector(0 to 31);
    >     SIGNAL index : INDX;
    > -- Some other declarations
    > Now, inside a process, I wish to examine the content of each location
    > in index - if it is '0'
    > do something as in:
    >
    > BEGIN
    >
    >     RAM_0 : PROCESS( WEB )
    >     VARIABLE cnt : INTEGER RANGE 0 TO 31;
    >
    >     BEGIN
    >     IF (WEB='1' AND WEB'EVENT )
    >      THEN IF (REB='0') THEN
    >          IF (index(0) = '0') THEN
    >            cnt := 0;
    >          END IF;
    >          --memory( CONV_INTEGER( A ) ) <= INN;
    >          END IF;
    >     END IF;
    >    END PROCESS RAM_0;
    >
    > I am getting an error message as:
    >         --> Run VHDL Compiler
    >         --> Compile file ram
    > parse    118 ERROR size of atom index_idx_0 should be static
    >
    > Any hints, suggestions would be of immense help. Thanks in advance for
    > your help.


    You dont make much sense, as there isnt anything wrong you the code
    you've posted. Are you trying to find the first index of a
    std_logic_vector that is '0'? or every index? What do you want to do
    when you've discovered one bit is '0'?
     
    Tricky, Nov 19, 2009
    #2
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  3. Daku

    Daku Guest

    On Nov 19, 1:50 pm, Tricky <> wrote:

    I want to iterate over each element of
    std_logic_vector, and depending on whether it is
    '1' or '0', do something else.

    > On 19 Nov, 04:28, Daku <> wrote:
    >
    >
    >
    > > Could some VHDL guru please help ? I am using the Alliance 5.0 tool. I
    > > have:

    >
    > > ARCHITECTURE dataflow_view OF ram IS
    > > SUBTYPE INDX IS std_logic_vector(0 to 31);
    > > SIGNAL index : INDX;
    > > -- Some other declarations
    > > Now, inside a process, I wish to examine the content of each location
    > > in index - if it is '0'
    > > do something as in:

    >
    > > BEGIN

    >
    > > RAM_0 : PROCESS( WEB )
    > > VARIABLE cnt : INTEGER RANGE 0 TO 31;

    >
    > > BEGIN
    > > IF (WEB='1' AND WEB'EVENT )
    > > THEN IF (REB='0') THEN
    > > IF (index(0) = '0') THEN
    > > cnt := 0;
    > > END IF;
    > > --memory( CONV_INTEGER( A ) ) <= INN;
    > > END IF;
    > > END IF;
    > > END PROCESS RAM_0;

    >
    > > I am getting an error message as:
    > > --> Run VHDL Compiler
    > > --> Compile file ram
    > > parse 118 ERROR size of atom index_idx_0 should be static

    >
    > > Any hints, suggestions would be of immense help. Thanks in advance for
    > > your help.

    >
    > You dont make much sense, as there isnt anything wrong you the code
    > you've posted. Are you trying to find the first index of a
    > std_logic_vector that is '0'? or every index? What do you want to do
    > when you've discovered one bit is '0'?
     
    Daku, Nov 19, 2009
    #3
  4. Daku

    KJ Guest

    On Nov 19, 5:38 am, Daku <> wrote:
    > On Nov 19, 1:50 pm, Tricky <> wrote:
    >
    > I want to iterate over each element of
    > std_logic_vector, and depending on whether it is
    > '1' or '0', do something else.
    >


    You would use a for loop to iterate over the range of a vector and an
    if statement to do conditional logic. An example below

    process(Clock)
    begin
    if rising_edge(Clock) then
    for Index in My_Vec'range loop
    if My_Vec(Index) = '1' then
    -- Do something
    else
    -- Do something else
    end if;
    end loop;
    end if;
    end process;

    Kevin Jennings
     
    KJ, Nov 19, 2009
    #4
  5. Daku

    Daku Guest

    I fully agree/understand and have tried out what you have said below,
    but I am getting an error
    message that does not make much sense to me. I
    am using the Alliance 5.0 toolset.
    I have :

    ENTITY ram IS
    port ( A : in std_logic_vector(0 to 31);
    CEB : in std_logic;
    WEB : in std_logic;
    REB : in std_logic;
    INN : in std_logic_vector(0 to 31);
    OUTT : out std_logic_vector(0 to 31)
    );
    END ram;

    ARCHITECTURE dataflow_view OF ram IS
    SUBTYPE INDX IS std_logic_vector(0 to 31);
    SIGNAL index : INDX;

    --Some other declarations

    BEGIN

    RAM_0 : PROCESS( WEB )
    VARIABLE cnt : INTEGER RANGE 0 TO 31;

    BEGIN
    IF (WEB='1' AND WEB'EVENT )
    THEN IF (REB='0') THEN
    IF (index(0) = '0') THEN
    cnt := 0;
    END IF;
    memory( CONV_INTEGER( A ) ) <= INN;
    END IF;
    END IF;
    END PROCESS RAM_0;

    -- Some other processes
    The compile time error message is:

    --> Run VHDL Compiler
    --> Compile file ram
    parse 118 ERROR size of atom index_idx_0 should be static

    Looks like it does not like : IF (index(0) = '0')

    Could someone please point out what exactly is the
    problem ?


    On Nov 19, 5:13 pm, KJ <> wrote:

    >
    > You would use a for loop to iterate over the range of a vector and an
    > if statement to do conditional logic. An example below
    >
    > process(Clock)
    > begin
    > if rising_edge(Clock) then
    > for Index in My_Vec'range loop
    > if My_Vec(Index) = '1' then
    > -- Do something
    > else
    > -- Do something else
    > end if;
    > end loop;
    > end if;
    > end process;
    >
    > Kevin Jennings
     
    Daku, Nov 20, 2009
    #5
  6. Daku

    StuartHobday

    Joined:
    Sep 22, 2009
    Messages:
    7
    Location:
    Dorset
    Index has been declared as an internal signal but where is it actually being assigned a value?

    Here is an example using a snippet from your code:

    index<= A;

    IndexTest : PROCESS( WEB )
    BEGIN
    ***IF (WEB='1' AND WEB'EVENT ) THEN
    ******IF (REB = '0') THEN
    *********IF (index(0) = '0') THEN
    ************OUTT<= INN;
    *********END IF;
    ******END IF;
    ***END IF;
    END PROCESS;

    Hopefully this will help!
     
    StuartHobday, Nov 20, 2009
    #6
  7. Daku

    Daku Guest

    I thank each one of you for your feedback. The really funny thing
    is that if I have :
    ARCHITECTURE dataflow_view OF ram IS
    SIGNAL index : std_logic_vector (0 to 31);

    Instead of :
    ARCHITECTURE dataflow_view OF ram IS
    SUBTYPE INDX IS std_logic_vector(0 to 31);
    SIGNAL index : INDX;

    Then the following compiles without a murmur of protest:
    RAM_0 : PROCESS( WEB )
    VARIABLE cnt : INTEGER RANGE 0 TO 31;

    BEGIN
    IF WEB='1' AND WEB'EVENT
    THEN IF REB='0' THEN
    FOR I IN index'RANGE LOOP
    IF index(I) = '0' THEN
    cnt := I;
    EXIT;
    END IF;
    END LOOP;
    memory( CONV_INTEGER( A ) ) <= INN;

    So right now I am hunting for a good VHDL simulator/verifier.
    Thank you all.


    On Nov 20, 3:18 pm, Alan Fitch <> wrote:
    > Daku wrote:
    > > I fully agree/understand and have tried out what you have said below,
    > > but I am getting an error
    > > message that does not make much sense to me. I
    > > am using the Alliance 5.0 toolset.
    > > I have :

    >
    > > ENTITY ram IS
    > > port ( A : in std_logic_vector(0 to 31);
    > > CEB : in std_logic;
    > > WEB : in std_logic;
    > > REB : in std_logic;
    > > INN : in std_logic_vector(0 to 31);
    > > OUTT : out std_logic_vector(0 to 31)
    > > );
    > > END ram;

    >
    > > ARCHITECTURE dataflow_view OF ram IS
    > > SUBTYPE INDX IS std_logic_vector(0 to 31);
    > > SIGNAL index : INDX;

    >
    > > --Some other declarations

    >
    > > BEGIN

    >
    > > RAM_0 : PROCESS( WEB )
    > > VARIABLE cnt : INTEGER RANGE 0 TO 31;

    >
    > > BEGIN
    > > IF (WEB='1' AND WEB'EVENT )
    > > THEN IF (REB='0') THEN
    > > IF (index(0) = '0') THEN
    > > cnt := 0;
    > > END IF;
    > > memory( CONV_INTEGER( A ) ) <= INN;
    > > END IF;
    > > END IF;
    > > END PROCESS RAM_0;

    >
    > > -- Some other processes
    > > The compile time error message is:

    >
    > > --> Run VHDL Compiler
    > > --> Compile file ram
    > > parse 118 ERROR size of atom index_idx_0 should be static

    >
    > > Looks like it does not like : IF (index(0) = '0')

    >
    > > Could someone please point out what exactly is the
    > > problem ?

    >
    > Hi Daku,
    > I think, as Mark says, the problem is the simulator. I had a look at
    > the Alliance toolset, and it seems to have two simulators. For one,
    > Asimut, it says
    >
    > "ASIMUT is not a powerfull VHDL simulator compared to industrial one. It
    > is used at LIP6 laboratory only for teaching purposes or small research
    > projets. For example it doesn't take benefit of vectorized expressions,
    > during compilation it splits them to an equivalent set of bits. During
    > the simulation it interprets all boolean expressions, it is not
    > effecient and it is very CPU time consuming compared to compiled and run
    > methods. Finally, the VHDL subset it accepts is not standard and is very
    > small. For example only boolean operators are supported, and only two
    > VHDL types can be used (bit and bit vectors). "
    >
    > For the other, VASY, it says
    >
    > "The VHDL compiler of VASY is very permissive and it doesn't verify the
    > correctness of the input description (according to the VHDL standard
    > reference manual). Another problem is that enumerate types are encoded
    > and they disappear in the resulting VHDL description. "
    >
    > VASY is also described as "It loads VHDL behavioral or structural
    > descriptions (written according to the Synopsys VHDL subset)." whatever
    > that means.
    >
    > So I would say "get a better simulator",
    >
    > Various FPGA vendors have free toolsets that contain VHDL simulators.
    >
    > regards
    > Alan
    >
    >
    >
    >
    >
    > > On Nov 19, 5:13 pm, KJ <> wrote:

    >
    > >> You would use a for loop to iterate over the range of a vector and an
    > >> if statement to do conditional logic. An example below

    >
    > >> process(Clock)
    > >> begin
    > >> if rising_edge(Clock) then
    > >> for Index in My_Vec'range loop
    > >> if My_Vec(Index) = '1' then
    > >> -- Do something
    > >> else
    > >> -- Do something else
    > >> end if;
    > >> end loop;
    > >> end if;
    > >> end process;

    >
    > >> Kevin Jennings

    >
    > --
    > Alan Fitch
    > Senior Consultant
    >
    > Doulos – Developing Design Know-how
    > VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
    > Services
    >
    > Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
    > 1AW, UK
    > Tel: + 44 (0)1425 471223 Email:
    > Fax: +44 (0)1425 471573 http://www.doulos.com
    >
    > ------------------------------------------------------------------------
    >
    > This message may contain personal views which are not the views of
    > Doulos, unless specifically stated.
     
    Daku, Nov 20, 2009
    #7
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