How to add delay in an output signal (without using clock) in cyclone 3 device?

Discussion in 'VHDL' started by pankaj.goel, Mar 17, 2009.

  1. pankaj.goel

    pankaj.goel

    Joined:
    Nov 24, 2008
    Messages:
    8
    Hi all,
    In my design, i have to introduce a delay of around 20-30 ns without using clock. I am using Cyclone 3 device. I tried it using lcells but even putting 40 lcells there in no delay at all when I see it at oscillosope. Can anybody suggest something?

    regards,
    pankaj
     
    pankaj.goel, Mar 17, 2009
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Roberto Gallo

    PCI core and Cyclone

    Roberto Gallo, Sep 15, 2003, in forum: VHDL
    Replies:
    2
    Views:
    796
    Roberto Gallo
    Sep 17, 2003
  2. Weng Tianxiang
    Replies:
    2
    Views:
    688
    Jonathan Bromley
    Jan 30, 2007
  3. TheThunder

    DCM clock signal output

    TheThunder, Jun 11, 2007, in forum: VHDL
    Replies:
    1
    Views:
    669
    Andy Peters
    Jun 12, 2007
  4. dibacco73
    Replies:
    1
    Views:
    696
    joris
    Feb 12, 2009
  5. Steffen Koepf
    Replies:
    1
    Views:
    678
    Mike Treseler
    Jan 20, 2010
Loading...

Share This Page