How to avoid this glitch

Discussion in 'VHDL' started by a82422@gmail.com, Dec 9, 2008.

  1. Guest

    Hi,guys:

    I got problem about this code, dout is my output data,when I wrote the
    following code, there are glitches on dout1,what should I do to avoid
    them? somebody told me to use the register,but how?
    thank you.

    dout1 <= dout and clk;
    dout2 <= (dout and clk) xor dout; // I want dout2 half clock period
    after dout1
     
    , Dec 9, 2008
    #1
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  2. wrote:

    > somebody told me to use the register,but how?
    > thank you.


    Design synthesis code by following
    a synchronous process template.
    Here's how I do it:
    http://mysite.verizon.net/miketreseler/
     
    Mike Treseler, Dec 9, 2008
    #2
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  3. MariuszK Guest

    On 9 Gru, 18:48, Mike Treseler <> wrote:
    > wrote:
    > > somebody told me to use the register,but how?
    > > thank you.

    >
    > Design synthesis code by following
    > a synchronous process template.
    > Here's how I do it:http://mysite.verizon.net/miketreseler/


    Mike,

    I like your "programing style" instead of long unreadible process with
    hundreds of signals assigments.
    Do you have any others examples?
    Do you have any others good, modern rules for VHDL programming?

    Best regards,
    Mariusz
     
    MariuszK, Dec 11, 2008
    #3
  4. MariuszK wrote:

    > I like your "programing style" instead of long unreadable process with
    > hundreds of signals assignments.


    Thanks. It is an unpopular style,
    but I don't like wasting code on wires.

    > Do you have any others examples?


    That is all of the public ones.
    Write me another and I'll put it up.

    > Do you have any others good, modern rules for VHDL programming?


    Learn your simulator first then write code
    that connotes what the logic *does*

    -- Mike Treseler
     
    Mike Treseler, Dec 11, 2008
    #4
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