How to avoid 'unable to synthesize' errors

Discussion in 'VHDL' started by Anon Anon, Mar 21, 2007.

  1. Anon Anon

    Anon Anon Guest

    Can somebody recommend a book or on-line document that explains how to
    avoid generating un-synthesizable code?

    I recently wrote some VHDL code that looked fine to me and was close to
    one of the Xilinx examples I'd seen, but it would not synthesize. I've
    fixed that problem now (by a complete re-write) but I'd like to avoid
    such problems in future and also get a clearer idea of what it is that
    causes such issues.

    Note that I am working in a Xilinx environment, using ISE 9.1.

    Many thanks for any help!

    AA
    Anon Anon, Mar 21, 2007
    #1
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  2. Anon Anon wrote:
    > Can somebody recommend a book or on-line document that explains how to
    > avoid generating un-synthesizable code?


    Google this group.

    Use a synchronous template.

    No wizards/generators for simple stuff.

    Verify functionality with vhdl simulation first.


    -- Mike Treseler
    Mike Treseler, Mar 21, 2007
    #2
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  3. Anon Anon schrieb:

    > Can somebody recommend a book or on-line document that explains how to
    > avoid generating un-synthesizable code?


    You have 3 things that you can model with a HDL: combinational logic,
    latches and flipflops:

    process(a,b)
    begin
    if (a='1') then
    logic<='0';
    else logic<=b;
    end if;
    end process;

    process(enable,data)
    begin
    if (enable='1') then
    latch<=data;
    end if;
    end process;

    process(async_reset,clock)
    begin
    if (async_reset='1') then
    flipflop<='0';
    elsif rising_edge(clock) then
    flipflop<=data;
    end if;
    end process;

    Three-state logic is something similar to combinational logic.

    There are a lot of ways how to model these things. You can even put
    everything into one process, as Mike Treseler suggests. I think for
    beginners it is often more clear what will be the result if one uses
    these templates.


    Ralf
    Ralf Hildebrandt, Mar 21, 2007
    #3
  4. Anon Anon

    Ahmed Samieh

    Joined:
    Mar 22, 2007
    Messages:
    4
    Last edited: Mar 22, 2007
    Ahmed Samieh, Mar 22, 2007
    #4
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