How to calculate the clock period?

[billys13]

Hi to everyone,

My question is how i can calculate the time between two events on a signal, and in particular on the clock signal. I mean, the time from when the clock becomes 1 until it becomes 0 again, that is the clock period. I would appreciate any help!

Thanks in advance!

Sorry for my english.

 

[jeppe]

You will need a "much faster" clock in order to do this.
Messure Clock = 100 MHz means your able to mesure a 1 MHz signal with 1% tolerance (or could it be 2%)

Jeppe

 

[billys13]

I'm sorry, i didn't understand. My question is if there is a function, or maybe if i can use a timer, in order to calculate in vhdl the time between two events on a signal. In particular, i want to calculate in vhdl code the exact time that takes for the clock signal to go from the high value (1) to the low value (0).

 

[jeppe]

Try to use this function.

S’LAST_ACTIVE
A function of the type TIME returning the time since the
the last update of the signal S.