how to convert an integer to std_logic_vector using vhdl

Discussion in 'VHDL' started by ashwin, Nov 22, 2005.

  1. ashwin

    ashwin Guest

    Hello everyone,
    I am trying to divite a std_logic_vector by a std_logic_vector.
    So i converted both of them into integers and divided. But how do i
    convert back to std_logic_vector.


    1) Is the integer type or the division" / " synthesizable in xilinx
    ISE.

    2) if i use integer as my output port and when i download my code onto
    the fpga, does it convert back to the binary. If yes to how many bits.


    I appreciate if you could answer these questions

    thanks
    Ashwin
     
    ashwin, Nov 22, 2005
    #1
    1. Advertising

  2. ashwin

    Andy Peters Guest

    ashwin wrote:
    > Hello everyone,
    > I am trying to divite a std_logic_vector by a std_logic_vector.
    > So i converted both of them into integers and divided. But how do i
    > convert back to std_logic_vector.


    Look up numeric_std -- this is the library that has the conversion
    functions you need. Do NOT use the obsolete std_logic_arith.

    > 1) Is the integer type or the division" / " synthesizable in xilinx
    > ISE.


    The answer is in the Xilinx XST documentation.

    > 2) if i use integer as my output port and when i download my code onto
    > the fpga, does it convert back to the binary. If yes to how many bits.


    Integers are 32 bit values.

    -a
     
    Andy Peters, Nov 22, 2005
    #2
    1. Advertising

  3. Andy Peters wrote:


    >> I am trying to divite a std_logic_vector by a std_logic_vector.
    >> So i converted both of them into integers and divided. But how do i
    >>convert back to std_logic_vector.

    >
    > Look up numeric_std -- this is the library that has the conversion
    > functions you need. Do NOT use the obsolete std_logic_arith.


    Full ack.

    my_int_u<=to_integer( unsigned(my_std_logic_vector) );
    my_int_s<=to_integer( signed(my_std_logic_vector) );



    >>2) if i use integer as my output port and when i download my code onto
    >>the fpga, does it convert back to the binary. If yes to how many bits.

    >
    > Integers are 32 bit values.


    Synthesis tools may be able to eliminate unneeded bits, IF it is clear
    to the tool. Therefore it is better to specify a "range" fo integers.

    In general it is not a good idea to use integers for (top level) ports,
    because often synthesis tools are configured to convert avery port
    signal to std_(u)logic_vector, because in reality you need a vector type
    for ports.

    Ralf
     
    Ralf Hildebrandt, Nov 22, 2005
    #3
  4. Jaakko Varteva, Nov 25, 2005
    #4
  5. ashwin

    Andy Peters Guest

    Ralf Hildebrandt wrote:

    > Synthesis tools may be able to eliminate unneeded bits, IF it is clear
    > to the tool. Therefore it is better to specify a "range" fo integers.


    Indeed, that's exactly what I do ... it's very helpful during
    simulation, as the tools will complain if you try to assign an
    out-of-range value.

    The synthesizer simply lops off whatever bits are not needed, and it
    all works well.

    > In general it is not a good idea to use integers for (top level) ports,
    > because often synthesis tools are configured to convert avery port
    > signal to std_(u)logic_vector, because in reality you need a vector type
    > for ports.


    I never use integers as ports, but I've used (numeric_std's) unsigned
    and signed (both of which are really std_logic_vectors in a different
    dress, anyways) as ports. A big downside to using ranged integers or
    naturals as ports is unsigned and signed can be assigned 'X' and 'Z'
    whereas integers cannot. This is very convenient when your inputs are
    from an ADC whose outputs can be tristated and you're doing math on
    these values. Saves a conversion.

    -a
     
    Andy Peters, Nov 28, 2005
    #5
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. jk
    Replies:
    3
    Views:
    10,822
    Amontec Team, Laurent Gauch
    Jan 14, 2004
  2. Sebastian Eggers

    Integer to std_logic_vector?

    Sebastian Eggers, Jun 30, 2005, in forum: VHDL
    Replies:
    10
    Views:
    39,272
    Fleetfoot
    Nov 21, 2011
  3. Replies:
    5
    Views:
    27,219
  4. Replies:
    3
    Views:
    11,549
    David Binnie
    Apr 30, 2006
  5. Thomas Rouam
    Replies:
    6
    Views:
    1,151
Loading...

Share This Page