how to convert signal value to integer

[Frank van Eijkelenburg]

Hi,

I'm new to VHDL and try to make some simple programs. Below I try to make an
entity that gives the contents of a specified address at the databus.
However, the compiler gives the following error:

# ERROR: C:/project/VHDL/project/sram/sram.vhd(58): Type error in variable
address. Needed type integer.

So the question is: how can I convert the value present at the address bus
to an integer? Or is there a better way to get this working??

TIA,
Frank

entity sram is
port(chip_enable : in bit;
output_enable : in bit;
address : in bit_vector (3 downto 0);
data : out std_logic_vector (3 downto 0));
end sram;

architecture behaviour of sram is
constant sram_size : Integer := 15;
type sram_mem is array (0 to sram_size) of std_logic_vector (0 to 3);
signal memory : sram_mem;

begin
get_data : process(address)
begin
if (chip_enable = '0' and output_enable = '0') then
-- get data from selected address
data <= memory(address);
else
data <= (others => 'Z');
end if;
end process;
end behaviour;

 

[Pieter Hulshoff]

So the question is: how can I convert the value present at the address bus

to an integer? Or is there a better way to get this working??

Use numeric_std from the IEEE library. You'll end up with something like:

data <= to_integer( unsigned( memory(address) ) );

Regards,

Pieter Hulshoff

 

[Mike Treseler]

Hi,

I'm new to VHDL and try to make some simple programs. Below I try to make an
entity that gives the contents of a specified address at the databus.
However, the compiler gives the following error:

For a related example see:


http://groups.google.com/groups?q=vhdl+test_oe_demo


-- Mike Treseler

 

[Pedro Claro]

what about conv_integer or to_integer?

Pedro Claro

 

[Yttrium]

why not using a function to convert the signal to int, something like

function vec2int (vec1: std_logic_vector) return integer is
variable retval: integer := 0;
alias vec: std_logic_vector(vec1'length-1 downto 0) is vec1;
begin
for i in vec'high downto 1 loop
if (vec(i)='1') then
retval:=(retval+1)*2;
else retval:=retval*2;
end if;
end loop;
if (vec(0)='1') then --we brengen de laatste bit in rekening door
eventueel op te tellen of niet!
retval:=retval+1;
end if;
return retval;
end vec2int;

and then use it like this: data <= memory(vec2int(address));

 

[vipinlal]

i think conv_integer should work in your case.
signal a : std_logic_vector (11 downto 0);
signal b: integer;
b<=conv_integer(a);

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