How to create a library for a Xilinx project

Discussion in 'VHDL' started by Weng Tianxiang, Oct 3, 2006.

  1. Hi,
    I have a project that have many files generated by Xilinx
    CoreGenerator.

    Now I put all those vhdl files generated by Xilinx CoreGenerator into
    my project.

    I want to put those files that never change into a library monitored by
    ModelSim software.

    I don't know how to create a ModelSim library.

    Please help.

    Thank you.

    Weng
     
    Weng Tianxiang, Oct 3, 2006
    #1
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  2. Weng Tianxiang

    Guest

    You have a 'gmail' address; surely you have heard of Google?

    Google search for "modelsim create library". The link you want is the
    2nd one.
     
    , Oct 3, 2006
    #2
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  3. Weng Tianxiang

    Jim Wu Guest

    vlib my_cores
    vlog -work my_cores core0.v

    HTH,
    Jim
    http://home.comcast.net/~jimwu88/tools/


    Weng Tianxiang wrote:
    > Hi,
    > I have a project that have many files generated by Xilinx
    > CoreGenerator.
    >
    > Now I put all those vhdl files generated by Xilinx CoreGenerator into
    > my project.
    >
    > I want to put those files that never change into a library monitored by
    > ModelSim software.
    >
    > I don't know how to create a ModelSim library.
    >
    > Please help.
    >
    > Thank you.
    >
    > Weng
     
    Jim Wu, Oct 3, 2006
    #3
  4. Jim Wu wrote:
    > vlib my_cores
    > vlog -work my_cores core0.v
    >
    > HTH,
    > Jim
    > http://home.comcast.net/~jimwu88/tools/
    >
    >
    > Weng Tianxiang wrote:
    > > Hi,
    > > I have a project that have many files generated by Xilinx
    > > CoreGenerator.
    > >
    > > Now I put all those vhdl files generated by Xilinx CoreGenerator into
    > > my project.
    > >
    > > I want to put those files that never change into a library monitored by
    > > ModelSim software.


    Hi Wu,
    I found the simplest way to create a library for a project while using
    ModelSim:
    1. Put all necessary *.vhd files into one proejct directory;
    2. Compile them without errors;
    3. Delete all *.vhd files that are generated by Xilinx CoreGenerator or
    something similar;

    These deleted *.vhd code are still referenced properly in the work
    library and there are no need to generate a separate library.

    Any comments?

    Thank you.

    Weng


    > >
    > > I don't know how to create a ModelSim library.
    > >
    > > Please help.
    > >
    > > Thank you.
    > >
    > > Weng
     
    Weng Tianxiang, Oct 3, 2006
    #4
  5. Jim Wu wrote:
    > vlib my_cores
    > vlog -work my_cores core0.v
    >
    > HTH,
    > Jim
    > http://home.comcast.net/~jimwu88/tools/
    >
    >
    > Weng Tianxiang wrote:
    > > Hi,
    > > I have a project that have many files generated by Xilinx
    > > CoreGenerator.
    > >
    > > Now I put all those vhdl files generated by Xilinx CoreGenerator into
    > > my project.
    > >
    > > I want to put those files that never change into a library monitored by
    > > ModelSim software.
    > >
    > > I don't know how to create a ModelSim library.
    > >
    > > Please help.
    > >
    > > Thank you.
    > >
    > > Weng
     
    Weng Tianxiang, Oct 3, 2006
    #5
  6. Weng Tianxiang

    Jim Wu Guest


    > I found the simplest way to create a library for a project while using
    > ModelSim:
    > 1. Put all necessary *.vhd files into one proejct directory;
    > 2. Compile them without errors;
    > 3. Delete all *.vhd files that are generated by Xilinx CoreGenerator or
    > something similar;
    >
    > These deleted *.vhd code are still referenced properly in the work
    > library and there are no need to generate a separate library.
    >
    > Any comments?



    Not sure what you're trying to do. If you just want to avoid
    re-compiling the core libraries, you don't have to delete the source
    files. What you can do is to do the compile in two steps:

    vlog -f my_core_files
    vlog -f my_design_files

    If you make any changes to your design files, you only need to run the
    second step.

    HTH,
    Jim
    http://home.comcast.net/~jimwu88/tools/


    > > > Weng
     
    Jim Wu, Oct 4, 2006
    #6
  7. Jim Wu wrote:
    > > I found the simplest way to create a library for a project while using
    > > ModelSim:
    > > 1. Put all necessary *.vhd files into one proejct directory;
    > > 2. Compile them without errors;
    > > 3. Delete all *.vhd files that are generated by Xilinx CoreGenerator or
    > > something similar;
    > >
    > > These deleted *.vhd code are still referenced properly in the work
    > > library and there are no need to generate a separate library.
    > >
    > > Any comments?

    >
    >
    > Not sure what you're trying to do. If you just want to avoid
    > re-compiling the core libraries, you don't have to delete the source
    > files. What you can do is to do the compile in two steps:
    >
    > vlog -f my_core_files
    > vlog -f my_design_files
    >
    > If you make any changes to your design files, you only need to run the
    > second step.
    >
    > HTH,
    > Jim
    > http://home.comcast.net/~jimwu88/tools/
    >
    >
    > > > > Weng


    Hi Jim,
    Thank you.

    Weng
     
    Weng Tianxiang, Oct 4, 2006
    #7
  8. Weng Tianxiang

    lolita

    Joined:
    Apr 6, 2009
    Messages:
    3
    help

    > > I want to put those files that never change into a library monitored by
    > > ModelSim software.
    > >
    > > I don't know how to create a ModelSim library.
    > >
    > > Please help.
    > >
    > > Thank you.
    > >
    > > Weng

    hi
    i want to see you for the creation of the library on modelsim is made automatiquemnt. you compile directly your files vhdl and it will post the following message for the first compilation:" work doesn't existing do you want to cerate?" you click on ok and you have your library.
    I have just worked on modelsim. now i try to synthesize with ISE (xilinx helps) but I don't know how to create the same library (work) in ISE.
    pls help me
    lolita
     
    lolita, Apr 6, 2009
    #8
  9. Weng Tianxiang

    lolita

    Joined:
    Apr 6, 2009
    Messages:
    3
    it's ok

    hi
    i want to see you for the creation of the library on modelsim is made automatiquemnt. you compile directly your files vhdl and it will post the following message for the first compilation:" work doesn't existing do you want to cerate?" you click on ok and you have your library.
    I have just worked on modelsim. now i try to synthesize with ISE (xilinx) but I don't know how to create the same library (work) in ISE.
    pls help me
    lolita


    it is ok, I found the solution on Internet to create a library on ISE(xilinx)
    good luck

    lolita
     
    lolita, Apr 6, 2009
    #9
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