how to declare array???

Discussion in 'VHDL' started by harish.avenue, Mar 15, 2012.

  1. harish.avenue

    harish.avenue

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    Pls help me in declaring and initializing an array of 10 elements & each of 32 bits in vhdl...
    harish.avenue, Mar 15, 2012
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  2. harish.avenue

    jeppe

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    jeppe, Mar 15, 2012
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  3. harish.avenue

    harish.avenue

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    can we initialize the array with the elements declared in the entity like, in my case i hv declared variables (arr0,arr1,arr2,arr3,arr4,arr5,arr6,arr7,arr8,arr9) with bit_vector(31 downto 0) in entity..
    ex:-

    type type_name is array(9 downto 0) of std_logic_vector(31 downto 0);
    signal sig_name : type_name:=(arr0,arr1,arr2,arr3,arr4,arr5,arr6,arr7,arr8,arr9);
    harish.avenue, Mar 16, 2012
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  4. harish.avenue

    jeppe

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    Well .... Bit_vector must then be converted to Std_Logic_vector.

    Or even better must Std_logic_vector be used at both declarations.
    jeppe, Mar 16, 2012
    #4
  5. harish.avenue

    harish.avenue

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    in the following code, does the array declaration is correct & does the function
    vect2int​
    help in converting the vector to integer, and will it assign the integer the values to k, maxvalue & minvalue...

    -------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;-- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    use IEEE.NUMERIC_STD.ALL;

    -- Uncomment the following library declaration if instantiating
    -- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity newcode is
    generic(N: integer:=9; M: integer:=31);
    Port ( clk : in STD_LOGIC;
    rst : in STD_LOGIC;
    start : in STD_LOGIC;
    pw0 : in bit_vector(M downto 0);
    pw1 : in bit_vector(M downto 0);
    pw2 : in bit_vector(M downto 0);
    pw3 : in bit_vector(M downto 0);
    pw4 : in bit_vector(M downto 0);
    pw5 : in bit_vector(M downto 0);
    pw6 : in bit_vector(M downto 0);
    pw7 : in bit_vector(M downto 0);
    pw8 : in bit_vector(M downto 0);
    pw9 : in bit_vector(M downto 0);

    ppr0 : in bit_vector(M downto 0);
    ppr1 : in bit_vector(M downto 0);
    ppr2 : in bit_vector(M downto 0);
    ppr3 : in bit_vector(M downto 0);
    ppr4 : in bit_vector(M downto 0);
    ppr5 : in bit_vector(M downto 0);
    ppr6 : in bit_vector(M downto 0);
    ppr7 : in bit_vector(M downto 0);
    ppr8 : in bit_vector(M downto 0);
    ppr9 : in bit_vector(M downto 0);

    cnt0: in bit_vector(M downto 0);
    cnt1: in bit_vector(M downto 0);
    cnt2: in bit_vector(M downto 0);
    cnt3: in bit_vector(M downto 0);
    cnt4: in bit_vector(M downto 0);
    cnt5: in bit_vector(M downto 0);
    cnt6: in bit_vector(M downto 0);
    cnt7: in bit_vector(M downto 0);
    cnt8: in bit_vector(M downto 0);
    cnt9: in bit_vector(M downto 0);

    opt_sgn : out bit);
    end newcode;

    architecture Behavioral of newcode is

    type ppr_arr is array(0 to N) of bit_vector(M downto 0);
    signal ppr : ppr_arr:=(ppr0,ppr1,ppr2,ppr3,ppr4,ppr5,ppr6,ppr7,ppr8,ppr9);

    type pw_arr is array(0 to N) of bit_vector(M downto 0);
    signal pw : pw_arr:=(pw0,pw1,pw2,pw3,pw4,pw5,pw6,pw7,pw8,pw9);

    type cnt_arr is array(0 to N) of bit_vector(M downto 0);
    signal cnt : cnt_arr:=(cnt0,cnt1,cnt2,cnt3,cnt4,cnt5,cnt6,cnt7,cnt8,cnt9);


    function vect2int(v: in bit_vector(M downto 0)) return integer is
    variable result:integer:=0;
    begin
    for i in 0 to M loop
    if v(i)='1' then
    result:=result+2**i;
    end if;
    end loop;
    return result;
    end vect2int;

    begin
    process(clk,start,rst)
    variable v1:bit:='0';
    variable k:natural:=0;
    variable count1:integer:=0;
    variable maxvalue1:integer:=0;
    variable maxvalue2:integer:=0;

    begin

    if(start='1' and rst='0') then
    if clk'event and clk='1' then
    for i in 0 to N loop

    k:=(vect2int(cnt(i)));
    maxvalue1:=(vect2int(pw(i)));
    maxvalue2:=(vect2int(pw(i)));

    for j in 0 to(vect2int(cnt(i))) loop

    v1:='1';
    if (count1<=maxvalue1) then
    count1:=count1 + 1;
    else
    count1:=0;
    end if;

    v1:='0';

    if (count1<=maxvalue2) then
    count1:=count1 + 1;
    else
    count1:=0;
    end if;
    end loop;
    end loop;
    end if;
    end if;
    opt_sgn <= v1;
    end process;

    end Behavioral;
    Last edited: Mar 16, 2012
    harish.avenue, Mar 16, 2012
    #5
  6. harish.avenue

    jeppe

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    It's seems your about to implement a C-program in VHDL and doing this must you keep in mind that C will translated into machine-code and executed by a Programmable Final State Machine = CPU.

    The VHDL program intended to be Hardware Description which translated into digital logic (perhaps a Non Programmable Final State Machine) which solves your task.

    Ok - it seems your only planing to read from the arrays in you program and hence will be allowed to initialize the array with concurrent code like.

    Arr(0) <= ppr0;
    Arr(1) <= ppr1;

    or perhaps even better, could you put this in a clock driven process in order to use F/F for storage.
    jeppe, Mar 17, 2012
    #6
  7. harish.avenue

    harish.avenue

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    Mar 15, 2012
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    ya i'm reading the array in order to compute the output...
    is that function correct?.... cant it be synthesisable?....will that convert the bitvector of 32bit in to an integer???
    harish.avenue, Mar 17, 2012
    #7
  8. harish.avenue

    jeppe

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    I would say yes ( this not your problem)

    The real problem will be if your algoritme is to complex.
    Your decided to use clock-driven process and you use variables as well - good :)
    But if the tasks in the loop actually require more then one clk-rising-edge will the
    synthesize fail and you will properly not be able to simulate eigter.

    Solution: Expand the loop into several states.
    Last edited: Mar 17, 2012
    jeppe, Mar 17, 2012
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