How to design 4 bit 4:1 multiplexer

Discussion in 'VHDL' started by Faisal Kabir, Oct 6, 2013.

  1. Faisal Kabir

    Faisal Kabir Guest

    Hello below is code for 1 bit 4:1 multiplexer. Can anybody tell me how to design 4 bit from 1 bit. Thanks



    // 4-to-1 multiplexer. Port list is taken exactly from
    // the I/O diagram.
    module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

    // Port declarations from the I/O diagram
    output out;
    input i0, i1, i2, i3;
    input s1, s0;

    // Internal wire declarations
    wire s1n, s0n;
    wire y0, y1, y2, y3;

    // Gate instantiations

    // Create s1n and s0n signals.
    not (s1n, s1);
    not (s0n, s0);

    // 3-input and gates instantiated
    and (y0, i0, s1n, s0n);
    and (y1, i1, s1n, s0);
    and (y2, i2, s1, s0n);
    and (y3, i3, s1, s0);

    // 4-input or gate instantiated
    or (out, y0, y1, y2, y3);

    endmodule

    // Define the stimulus module (no ports)
    module stimulus;

    // Declare variables to be connected
    // to inputs
    reg IN0, IN1, IN2, IN3;
    reg S1, S0;

    // Declare output wire
    wire OUTPUT;

    // Instantiate the multiplexer
    mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);

    // Stimulate the inputs
    initial
    begin
    // set input lines
    IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
    #1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);


    // choose IN0
    S1 = 0; S0 = 0;
    #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

    // choose IN1
    S1 = 0; S0 = 1;
    #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

    // choose IN2
    S1 = 1; S0 = 0;
    #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

    // choose IN3
    S1 = 1; S0 = 1;
    #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
    end

    endmodule
    Faisal Kabir, Oct 6, 2013
    #1
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  2. Faisal Kabir

    Jim Lewis Guest

    Simple, use type std_logic_vector on your ports rather than std_logic. :).

    Try comp.lang.verilog for an answer in Verilog.
    Jim Lewis, Oct 8, 2013
    #2
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