How to design a 16 bit CISC processor ?

[YacentY]

I'm student of Univeristy of Technology in Poland
My task is to design a 16 bit CISC processor in VHDL or Verilog language
I know how to do this in theory but it is a black magic form me to create it
in VHDL or Verilog
I know basics of ModelSim VHDL
I created some simple hardware parts
Does anyone know a site where I can find help
or somebody maybe will give me some instructions

// Helpless Student

 

[Mike Treseler]

I'm student of Univeristy of Technology in Poland
My task is to design a 16 bit CISC processor in VHDL or Verilog language
I know how to do this in theory but it is a black magic form me to create it
in VHDL or Verilog
I know basics of ModelSim VHDL
I created some simple hardware parts
Does anyone know a site where I can find help
or somebody maybe will give me some instructions

// Helpless Student

I suggest you either get this project
changed to something that interests you
or drop the class. The world doesn't need
any more bad CPU cores or helpless engineers.


-- Mike Treseler

 

[Ralf Hildebrandt]

I'm student of Univeristy of Technology in Poland
My task is to design a 16 bit CISC processor in VHDL or Verilog language

Isn't it a little bit tough for a class project?
(I took 6 Months (8h/day) for a 16 Bit RISC core with known instruction
set and the solution was not really satisfiying.)

I know how to do this in theory but it is a black magic form me to create it
in VHDL or Verilog

First of all: Think about the instruction set.
Then: Think about a data path, that fits to the instruction set.
Think about how to compute every instruction on the chosen data path.
(Think about state machines and register-transfer-lists.)

I know basics of ModelSim VHDL
I created some simple hardware parts

If you know, what you have to model (an ALU, a bus system, the
registers, the main state machine ....) it is relatively easy to have
the idea how to implement in an a HDL. (Many problems will occur and the
final description is not easy, but the idea what a component can be in
real hardware is relatively easy.)



Ralf

 

[MM]

Take a look at the www.opencores.org However, your task seems to be too
complex for your level....

/Mikhail

 

[MM]

I suggest you either get this project
changed to something that interests you
or drop the class. The world doesn't need
any more bad CPU cores or helpless engineers.


-- Mike Treseler

Mike,

Are you having a bad day ? ) Take it easy...

/Mikhail

 

[YacentY]

I'm student of Univeristy of Technology in Poland

My task is to design a 16 bit CISC processor in VHDL or Verilog language
I know how to do this in theory but it is a black magic form me to create it
in VHDL or Verilog
I know basics of ModelSim VHDL
I created some simple hardware parts
Does anyone know a site where I can find help
or somebody maybe will give me some instructions

// Helpless Student

today I was talking with my professor and he said that I had to simulate
only my processor.
I've done instruction set, I thought about architecture so I think
theoretical i have that processor how can I do it in verilog or VHDL?? which
one will be easiest??

 

[Milos]

If You only need to simulate the porcessor, then You can take a look
at the FMF model library
www.eda.org/fmf
Look for processor models. There are some VHDL VITAL models that You
may be able to use.

p89c51 for examp...

http://www.eda.org/fmf/fmf_public_models/proc/

 

[Ralf Hildebrandt]

today I was talking with my professor and he said that I had to simulate
only my processor.

Umm .. well if I mix up the words, I get:

"..he said, that I only had to simulate my processor"

(Could it be a translation mistake? Otherwise Your task would not be
"smaller" than before.)

It makes a big difference if you only have to simulate it or have to
model it synthesizable.

I've done instruction set, I thought about architecture so I think
theoretical i have that processor how can I do it in verilog or VHDL??

Split all into pieces. (It's like a house, that is build of many pieces.)

Describe these pieces (components). Connect the pieces to bigger blocks.

which one will be easiest??

It does not matter if you chose Verilog or VHDL. Some people like
Verilog more, some VHDL. (I for myself prefer VHDL.)
Nevertheless ... all can be written in both languages.

For any HDL it is highlig recommended to read a beginners book. "HDL
chip design" ( http://www.doone.com/hdl_chip_des.html ) was very helpful
for me. I covers every example in Verilog in VHDL (if possible).

Ralf

 

[A. Tomaszewski]

Myself, I can only say this:

http://www.pjrc.com/tech/osu8/index.html

This is the best webpage on microprocessor design I have managed to
find over a very long period of time. Make most of it.

T.

 

[A. Tomaszewski]

I suggest you either get this project
changed to something that interests you
or drop the class. The world doesn't need
any more bad CPU cores or helpless engineers.


-- Mike Treseler

Sure boss.

Andrew

 

[Wong]

Take a look at the www.opencores.org However, your task seems to be too
complex for your level....

What about ARM 7/9 cores for intermediate level in FPGA ?

 

[john jakson]

Myself, I can only say this:

http://www.pjrc.com/tech/osu8/index.html

This is the best webpage on microprocessor design I have managed to
find over a very long period of time. Make most of it.

T.

You jest surely

I am really glad I never saw that webpage when I started out 30yrs
ago, would have confused the heck out of me. Glad the web didn't exist
then too. Seems like the web gives anyone with no clue the chance to
author nonsense.

Seriously, there are alot of good materials out there on paper,
probably in your library. Since you indicate 16bits, how about looking
over the pdp11, or ti9900. You could drop quite a few features, only
implement 16bit operands, 2 or 3 address modes etc, ignore the io
parts. The old DEC,TI,DG books practically spell out the architecture.
If you got one of the classics half running, you might also dig up
some old sw tools,

A cpu design is not complete or worth anything without sw tools, use
an ISA that aleady exists and likely sitting in the dept basement and
your half way done.

You can also look for emulators for alot of old machines that may run
on pc, alot easier than firing up rusty old iron. Now you can write,
run test programs on pc emulator for ancientISA and run same on HDL
model without leaving chair. Practically every CISC ISA has an
emulator for it somewhere on the web. If you have the source, you can
even treat it as the microcode for that cpu ISA that just happens to
use x86 or whatever as a host.

If you are open to Verilog, at least 2 of the texts in my collection
cover cpu design, but they are in Boston & I am not so the titles
escape me. One is elementary level describing cpu in various styles
(Eli Stern..?), and the other (German? Uho..) describes in more detail
a cpu that has been prototyped. Amazon search may help find them.

good luck

johnjaksonATusaDOTcom