How to do the shift bit operation in Array

[ZHIQUAN]

type B_Matrix is array (0 to 3) of std_logic_vector(15 downto 0);
signal MatrixB : B_Matrix :=(others =>(others=>'0'));

For example MatrixB has some values {"1000001010101010",
"1000001010111010",..........}

Now I want to get the first bit of MatrixB(2) to give variable ad like
that: ad := MatrixB(2, 15); It doesn't work. Sounds like I use the
wrong grammar. Does anybody know how to do that.

One more thing, Can I do the operation like :

d2Rkk is signed(17 downto 0):= (others=>'0');

d2Rkk (12 downto 0) :=signed(MatrixR(2, 15 downto 3));

It looks like if the variable is an array type, the element of the
array cannot do the normal operation as if they are independent ones. I
mean if MatrixR is std_logic_vector (15 downto 3), I can just do d2Rkk
(12 downto 0) :=signed(MatrixR( 15 downto 3)); Where I can find some
examples for array operations ? Thanks.

 

[Andy]

You index an array of arrays (slv is an array) as MatrixB(2)(15), not
(2,15).
Two-dimensional arrays are allowed in vhdl, but not synthesizable.
Arrays of arrays are allowed and synthesizable.

Andy

 

[Rob Dekker]

Two-dimensional arrays are allowed in vhdl, but not synthesizable.
Arrays of arrays are allowed and synthesizable.

Multi-dimensional arrays in VHDL should be synthesizable.
Which tool did you find that does not support that ?

Rob

 

[Andy]

To be honest, I have not tried multidimensional arrays in a long time,
but synplicity did not support it, and I don't think they do now. Have
you found any that do?

I always use arrays of arrays (of arrays of...) . It gives you more
flexibility anyway.

matrix(2)(15 downto 8) <= a_byte;

matrix(3 downto 1) <= three_words;

matrix(3 downto 1)(15 downto 8) <= no_worky; -- three_bytes won't work

Those operations don't work with multidimensional arrays.

Besides, any multidimensional array can be represented as an array of
arrays (of...).

Andy

 

[ZHIQUAN]

So I cannot use it like MatrixA)(17) <=MatrixB(1)(15) ？Error: parse
error, unexpected COLON

 

[ZHIQUAN]

I cannot do like this: MatrixA(0 to 3)(17 downto 16)<= (others=>
MatrixB(0 to 3)(15));

MatrixA is array(integer range 0 to 3) of std_logic_vector (17 downto
0);
MatrixB is array(integer range 0 to 3) of std_logic_vector(15 downto
0);

Besides, I cannot use ":" to replace (0 to 3).

 

[Rob Dekker]

To be honest, I have not tried multidimensional arrays in a long time,
but synplicity did not support it, and I don't think they do now. Have
you found any that do?

Yes. Leonardo for sure. I wrote the synthesizer for it.
And Quartus II does, since is has a Verific front-end.
I would be surprised if Synplicity does not support it (at least now)

I always use arrays of arrays (of arrays of...) . It gives you more
flexibility anyway.

matrix(2)(15 downto 8) <= a_byte;

matrix(3 downto 1) <= three_words;

matrix(3 downto 1)(15 downto 8) <= no_worky; -- three_bytes won't work

Those operations don't work with multidimensional arrays.

Besides, any multidimensional array can be represented as an array of
arrays (of...).

You are right. Array-of-array has everything that 2-dim array has, and more.
I don't know why they even introduced the concept (of multi-dim arrays).
But is is there in the language, so tools should support it.

Rob

 

[Rob Dekker]

I cannot do like this: MatrixA(0 to 3)(17 downto 16)<= (others=>
MatrixB(0 to 3)(15));

MatrixA is array(integer range 0 to 3) of std_logic_vector (17 downto
0);
MatrixB is array(integer range 0 to 3) of std_logic_vector(15 downto
0);

So you want to assign a few bits of each of the 4 elements of MatrixA
You cannot do that with the 0 to 3 slice as far as I know.
Please use a for-loop.

Besides, I cannot use ":" to replace (0 to 3).

What made you think that the ":" does anything other than give you a syntax error ?

 

[Mike Treseler]

Yes. Leonardo for sure. I wrote the synthesizer for it.

Congratulations.
That's the first synthesizer I used that
really covered VHDL-87.

And Quartus II does, since is has a Verific front-end.

Interesting. Do you think the register duplication
issue we discussed in another thread could ever be fixed
in the front end, or will that always have to be
taken out by the fitter?

-- Mike Treseler

 

[Rob Dekker]

Congratulations.
That's the first synthesizer I used that
really covered VHDL-87.

Thanks !
The first implementation I did was quite terrible (back in '91-92), but after two rewrites it got pretty good..
Those were the days..

Interesting. Do you think the register duplication
issue we discussed in another thread could ever be fixed
in the front end, or will that always have to be
taken out by the fitter?

I am sorry Mike. Which thread was that ?

 

[Mike Treseler]

Which thread was that ?

http://tinyurl.com/39wllq


-- Mike Treseler

 

[Rob Dekker]

http://tinyurl.com/39wllq

You mean this remark from Jim ? :
....
By the way, I am still waiting for vendors to support multiple
clocked FIFOs and registers. I know that Xilinx at one time
supported a coding style that uses VHDL-93 shared variables,
however, as of VHDL-2000/2002, shared variables must be a
protected type.
....

I think that refers to DDR (double-data rate) register inference..
We (Jim and me) had a great conversation about that one time (I'll find it if this is the topic you meant).

-----
Interesting thread though ! I am sorry I missed it.
On the subject of synthesizability of RTL construct, there is certainly a mismatch with what the tools can do, what the committees
say the rules are, and what the designers are doing.
The thread clearly points that out. For example : mixed blocking and non-blocking assignments. Even Cliff's report mentiones that
the following code is not synthesizable (because of mixed blocking and non-blocking assignment onto q) :

module ba_nba6 (q, a, b, clk, rst_n);
output q;
input a, b, rst_n;
input clk;
reg q, tmp;
always @(posedge clk or negedge rst_n)
if (!rst_n)
q = 1'b0; // blocking assignment to "q"
else begin
tmp = a & b;
q <= tmp; // nonblocking assignment to "q"
end
endmodule

There is no reason why this would be non-synthesizable, and we synthesize it just fine..
And designers are using it too ! (They typically use whatever the tools are not complaining about).
However, Synopsys errors out. And so do many other tools.
Trying to standardize the concept of synthesizability is very, very difficult. So I do not envy Jim.
I was part of 1076.6 in the early days. There is a lot of politics going on in defining a standard, and in the end you can only
standardize the weakest link (or the biggest link).

Regards

Rob

 

[ZHIQUAN]

Thanks. I just start to learn how to code vhdl to implementation
algorithm. Actually I am not very familiar with the use of coding vhdl.
Sometimes I assume one grammar can be used for another thing. It is
difficult for me to explain why I try this. I tried everything to see
how it works.

I have done my algorithm implementation in serial structure. The
throughput is unfortunately very low. I want to improve its throughput.
Therefore I am thinking to replace some RAM by Array, then I possibly
can write/read many data in one clock cycle. I only knew a little bit
about the Array. Need learn more. There's a really good vibe to here,
though I cannot always understand what you all are talking about
^ ^