how to enter this bus notation

[pfrogge]

Hi, trying to transition from verilog RTL design, in that language I could create a bus that was a mixture of constants and variables as follows, how can I do this in VHDL?

{1,0,CS0,1,0,0,CLK,1,0}

thanks in advance.

 

[flymolo]

You can do it in many ways. I guess the most straightforward is:

'1' & '0' & CS0 & '1' & '0' & '0' & CLK & '1' & '0'

you can group constants:

b"10" & CS0 & b"100" & CLK & b"10"

 

[pfrogge]

much appreciated,
thanks