how to enter this bus notation

Discussion in 'VHDL' started by pfrogge, Jun 13, 2011.

  1. pfrogge

    pfrogge

    Joined:
    Jun 13, 2011
    Messages:
    2
    Hi, trying to transition from verilog RTL design, in that language I could create a bus that was a mixture of constants and variables as follows, how can I do this in VHDL?

    {1,0,CS0,1,0,0,CLK,1,0}

    thanks in advance.
     
    pfrogge, Jun 13, 2011
    #1
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  2. pfrogge

    flymolo

    Joined:
    Jun 2, 2011
    Messages:
    10
    You can do it in many ways. I guess the most straightforward is:
    Code:
    '1' & '0' & CS0 & '1' & '0' & '0' & CLK & '1' & '0'
    you can group constants:
    Code:
    b"10" & CS0 & b"100" & CLK & b"10"
     
    flymolo, Jun 20, 2011
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  3. pfrogge

    pfrogge

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    Jun 13, 2011
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    much appreciated,
    thanks
     
    pfrogge, Jun 20, 2011
    #3
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