How to exchange a string between a

Discussion in 'VHDL' started by Eric, Sep 15, 2006.

  1. Eric

    Eric Guest

    Hi,

    I would to setup a verification methodology in which a device read the
    stimuli from a file given a filename and in which the filename can be
    changed several time during the simulation (in order to execute several
    test scenario one after the other). I encounter some problems in
    passing the filename to the device because the VHDL compiler that I use
    (modelsim) only accept to pass a fixed length string to the device.

    Could someone help me in finding a(n elegant) workaround?

    Many thanks.

    Eric

    -- In the appropriate package
    TYPE xl_handler_type IS RECORD
    filename : STRING;
    END RECORD xl_handler_type;

    -- The testbench looks like this.
    ENTITY testbench IS
    GENERIC(filename: STRING); -- defined via the command-line args
    when simulating
    END ENTITY testbench;

    ARCHITECTURE b OF testbench IS
    SIGNAL xl_handler : xl_handler_type;
    BEGIN
    PROCESS
    BEGIN
    -- set a filename to be used by the device
    WAIT -- for some time
    -- set another filename to be used by the device
    WAIT -- for some more time
    END PROCESS;
    duv: device
    PORT MAP(xl_handler => xl_handler);
    END ARCHITECTURE b;

    -- The device looks like this.
    ENTITY device IS
    PORT(xl_handler : INOUT xl_handler_type);
    END ENTITY device;

    ARCHITECTURE b OF device IS
    BEGIN
    main: PROCESS(clk)
    BEGIN
    -- I open the file whose name is transmitted using xl_handler
    .... but how?
    END PROCESS main;
    END ARCHITECTURE b;
    Eric, Sep 15, 2006
    #1
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  2. Eric

    KJ Guest

    Eric wrote:
    > Hi,
    >
    > I would to setup a verification methodology in which a device read the
    > stimuli from a file given a filename and in which the filename can be
    > changed several time during the simulation (in order to execute several
    > test scenario one after the other). I encounter some problems in
    > passing the filename to the device because the VHDL compiler that I use
    > (modelsim) only accept to pass a fixed length string to the device.
    >
    > Could someone help me in finding a(n elegant) workaround?
    >
    > Many thanks.
    >
    > Eric
    >

    Couple suggestions:

    Instead of passing the filename down through the food chain, you might
    instead want to open the file in the testbench and then pass a FILE
    type instead. This would require changing the 'xl_handler' type.
    TYPE xl_handler_type IS RECORD
    file_type : FILE of whatever type you're using;
    END RECORD xl_handler_type;

    If you want to keep the filename in the xl_handler record then you have
    to pass it a fixed length string (as you've found out) so you have to
    predefine a string size that is long enough for all cases and when you
    go to modifying it in your testbench you'll need to set the entire
    string.

    If you're using Modelsim, you might want to look into the std_iopak
    library which should be one of the default libraries that are already
    installed. (Other simulators probably have something similar). That
    library has functions like 'strcat', 'strcpy', 'strlen', etc. that work
    much like the 'C' language functions of the same name. That makes it
    easier to copy variable length strings into a fixed sized string,
    appends the trailing NUL character and such.

    KJ
    KJ, Sep 15, 2006
    #2
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  3. Eric

    Eric Guest

    Hi,

    unfortunately, it does not work because I'm not allowed to use a FILE
    in the record.

    I tried:
    TYPE xl_handler_i_type IS RECORD
    file_desc : FILE OF STRING;
    END RECORD xl_handler_i_type;

    vcom error message:
    near "FILE": expecting: STRING IDENTIFIER
    near "file_type": expecting: END

    then I tried:
    TYPE aaaa IS FILE OF STRING;
    TYPE xl_handler_i_type IS RECORD
    file_desc : aaaa;
    END RECORD xl_handler_i_type;

    vcom error message:
    (vcom-1187) Elements of file type are not allowed in composite
    types.
    Eric, Sep 15, 2006
    #3
  4. Eric

    KJ Guest

    Eric wrote:
    > Hi,
    >
    > unfortunately, it does not work because I'm not allowed to use a FILE
    > in the record.
    >


    Well sometimes I do give bum advice.

    Try option 2 that I gave you then and just define a 'big' string in the
    record type and use the 'strcpy', et al functions to make life easier.

    KJ
    KJ, Sep 15, 2006
    #4
  5. Eric a écrit :
    > Hi,
    >
    > I would to setup a verification methodology in which a device read the
    > stimuli from a file given a filename and in which the filename can be
    > changed several time during the simulation (in order to execute several
    > test scenario one after the other). I encounter some problems in
    > passing the filename to the device because the VHDL compiler that I use
    > (modelsim) only accept to pass a fixed length string to the device.
    >
    > Could someone help me in finding a(n elegant) workaround?


    Hi
    An easy solution would be to have all file names the same length. I
    tried it and it works fine.
    Another solution where you read your file names from another file would
    copy the file name to a new line and then call a procedure (called
    file_open, a fine example of overloading) defined as follows :

    procedure file_open(file f : text; name : in line; kind : in
    file_open_kind) is
    variable filename : string(1 to name'length);
    begin
    for i in name'range loop
    filename(i) := name(i);
    end loop;
    file_open(f, filename, kind);
    end procedure file_open;

    Nicolas
    Nicolas Matringe, Sep 15, 2006
    #5
  6. Eric

    amakyonin Guest

    Eric wrote:
    > Hi,
    >
    > I would to setup a verification methodology in which a device read the
    > stimuli from a file given a filename and in which the filename can be
    > changed several time during the simulation (in order to execute several
    > test scenario one after the other). I encounter some problems in
    > passing the filename to the device because the VHDL compiler that I use
    > (modelsim) only accept to pass a fixed length string to the device.
    >
    > Could someone help me in finding a(n elegant) workaround?


    You can use an access to an unconstrained string type as a way to work
    with variable length strings. The textio package has the LINE type
    defined this way. You could also define your own access type or alias
    LINE to something else.

    use ieee.textio.all;
    TYPE xl_handler_type IS RECORD
    filename : LINE;
    END RECORD xl_handler_type;


    To use this you need to allocate the string in the record before you
    pass it on to a procedure:

    xl_handler.filename = new string'(filename);

    You can use the .all method to retrieve the string from the access
    type:

    file_open(status, fh, xl_handler.filename.all, mode);

    Finally. Remember to deallocate the string when you're done with it.

    deallocate(xl_handler.filename);
    amakyonin, Sep 18, 2006
    #6
  7. Eric

    Duane Clark Guest

    Eric wrote:
    > Hi,
    >
    > I would to setup a verification methodology in which a device read the
    > stimuli from a file given a filename and in which the filename can be
    > changed several time during the simulation (in order to execute several
    > test scenario one after the other). I encounter some problems in
    > passing the filename to the device because the VHDL compiler that I use
    > (modelsim) only accept to pass a fixed length string to the device.
    >


    The way I do it is to declare a large enough string for any filename in
    a package file:
    subtype Filename_Str_Type is String(1 to 50);

    I am reading a filename out of a plain text script file, so when I do
    that, as I copy the filename into the string, I count the number of
    characters copied:

    -- Skip leading spaces/tabs, then copy characters into the
    -- output string until the next space/tab.
    procedure get_filename(L : inout line;
    the_str : inout Filename_Str_Type;
    name_len : inout integer) is
    variable the_ch : character;
    begin
    j := 1;
    read(L, the_ch, good);
    -- skip leading spaces and tabs
    while good = True and (the_ch = ' ' OR the_ch = ht) loop
    read(L, the_ch, good);
    end loop;
    -- get the string
    while good = True and j <= the_str'length loop
    the_str(j) := the_ch;
    j := j+1;
    read(L, the_ch, good);
    if the_ch = ' ' OR the_ch = ht then
    exit;
    end if;
    end loop;
    name_len := j;
    end procedure get_filename;

    Which is called like:

    get_filename(L, file_str, name_len_v);
    data_filename <= file_str;
    NAME_LEN <= name_len_v;

    I output the filename string and the number of characters in it:

    entity bd_test is
    port (
    data_filename : out Filename_Str_Type;
    NAME_LEN : out integer;

    And then the file is opened in another place like this:

    file_open(data_file, external_name => data_filename(1 to
    NAME_LEN), open_kind => read_mode);
    Duane Clark, Sep 18, 2006
    #7
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