How to extract subarray ?

Discussion in 'VHDL' started by Daku, Nov 15, 2009.

  1. Daku

    Daku Guest

    My VHDL is a bit rusty and maybe this is a very silly question. I wish
    to do the following - suppose I have:
    A : in std_logic_vector(7 downto 0);
    How do I extract say bits 3 -> 0 ? Is there any notion of
    concatenating registers as in Verilog ?
    Any hints, suggestions would be greatly appreciated.
    Thanks in advance for your help.
    Daku, Nov 15, 2009
    #1
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  2. On Nov 15, 4:46 am, Daku <> wrote:
    > My VHDL is a bit rusty and maybe this is a very silly question


    Not silly, just rather basic!

    >  A : in std_logic_vector(7 downto 0);
    > How do I extract say bits 3 -> 0 ?


    Much the same as Verilog:

    lower_nybble <= A(3 downto 0);

    > Is there any notion of
    > concatenating registers as in Verilog ?


    Of course.

    Verilog:
    my_bag_o_bits = { A[7], A[3:2], A[0] };

    VHDL:
    my_bag_o_bits <= A(7) & A(3 downto 2) & A(0);

    Terrible trap for the unwary programmer who works in both
    VHDL and Verilog: the "&" operator in VHDL is concatenation,
    and most certainly does NOT mean logical-and!!!!
    --
    Jonathan Bromley
    Jonathan Bromley, Nov 15, 2009
    #2
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