How to extract subarray ?

D

Daku

My VHDL is a bit rusty and maybe this is a very silly question. I wish
to do the following - suppose I have:
A : in std_logic_vector(7 downto 0);
How do I extract say bits 3 -> 0 ? Is there any notion of
concatenating registers as in Verilog ?
Any hints, suggestions would be greatly appreciated.
Thanks in advance for your help.
 
J

Jonathan Bromley

My VHDL is a bit rusty and maybe this is a very silly question

Not silly, just rather basic!
 A : in std_logic_vector(7 downto 0);
How do I extract say bits 3 -> 0 ?

Much the same as Verilog:

lower_nybble <= A(3 downto 0);
Is there any notion of
concatenating registers as in Verilog ?

Of course.

Verilog:
my_bag_o_bits = { A[7], A[3:2], A[0] };

VHDL:
my_bag_o_bits <= A(7) & A(3 downto 2) & A(0);

Terrible trap for the unwary programmer who works in both
VHDL and Verilog: the "&" operator in VHDL is concatenation,
and most certainly does NOT mean logical-and!!!!
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

Forum statistics

Threads
473,744
Messages
2,569,483
Members
44,901
Latest member
Noble71S45

Latest Threads

Top