D
Daku
My VHDL is a bit rusty and maybe this is a very silly question. I wish
to do the following - suppose I have:
A : in std_logic_vector(7 downto 0);
How do I extract say bits 3 -> 0 ? Is there any notion of
concatenating registers as in Verilog ?
Any hints, suggestions would be greatly appreciated.
Thanks in advance for your help.
to do the following - suppose I have:
A : in std_logic_vector(7 downto 0);
How do I extract say bits 3 -> 0 ? Is there any notion of
concatenating registers as in Verilog ?
Any hints, suggestions would be greatly appreciated.
Thanks in advance for your help.