How to force an internal wire which is deep inside DUT hierachy attop level testbench using VHDL des

Discussion in 'VHDL' started by One Cent, Jul 2, 2009.

  1. One Cent

    One Cent Guest

    Hi,
    I am interested to know how can i force an internal wire which is deep
    inside DUT hierachy at top level testbench using VHDL design?
    In verilog, i can write in this way at top level testbench as below:

    initial
    begin
    force tb.design.memory.rx_buffer.enable_model = 1'b0;
    #100;
    force tb.design.memory.rx_buffer.enable_model = 1'b1;
    end

    But how can I do this in a VHDL testbench?

    Thanks.
     
    One Cent, Jul 2, 2009
    #1
    1. Advertising

  2. One Cent

    backhus Guest

    Re: How to force an internal wire which is deep inside DUT hierachyat top level testbench using VHDL design?

    On 2 Jul., 03:58, One Cent <> wrote:
    > Hi,
    > I am interested to know how can i force an internal wire which is deep
    > inside DUT hierachy at top level testbench using VHDL design?
    > In verilog, i can write in this way at top level testbench as below:
    >
    > initial
    > begin
    >  force tb.design.memory.rx_buffer.enable_model = 1'b0;
    >  #100;
    >   force tb.design.memory.rx_buffer.enable_model = 1'b1;
    > end
    >
    > But how can I do this in a VHDL testbench?
    >
    > Thanks.


    Hi,
    if you are using Modelsim you can use the SignalSpy functions.
    There you can access signals(wires/regs) by providing their
    hierarchical path in the system.
    Do a search for it in the documentation. It's all well explained.

    Have a nice simulation
    Eilert
     
    backhus, Jul 2, 2009
    #2
    1. Advertising

  3. One Cent

    cheevu

    Joined:
    Jan 9, 2008
    Messages:
    5
    Location:
    BAngalore
    use signal_force to force the signal..
    U need to use modelsim library.
     
    cheevu, Jul 2, 2009
    #3
  4. One Cent

    One Cent Guest

    Re: How to force an internal wire which is deep inside DUT hierachyat top level testbench using VHDL design?

    On Jul 2, 2:50 pm, backhus <> wrote:
    > On 2 Jul., 03:58, One Cent <> wrote:
    >
    > > Hi,
    > > I am interested to know how can i force an internal wire which is deep
    > > inside DUT hierachy at top level testbench using VHDL design?
    > > In verilog, i can write in this way at top level testbench as below:

    >
    > > initial
    > > begin
    > >  force tb.design.memory.rx_buffer.enable_model = 1'b0;
    > >  #100;
    > >   force tb.design.memory.rx_buffer.enable_model = 1'b1;
    > > end

    >
    > > But how can I do this in a VHDL testbench?

    >
    > > Thanks.

    >
    > Hi,
    > if you are using Modelsim you can use the SignalSpy functions.
    > There you can access signals(wires/regs) by providing their
    > hierarchical path in the system.
    > Do a search for it in the documentation. It's all well explained.
    >
    > Have a nice simulation
    >   Eilert


    Thanks Eilert!
    This reminds me the use of init_signal_spy function in Modelsim!!
    Thanks again =)
     
    One Cent, Jul 3, 2009
    #4
  5. One Cent

    HT-Lab Guest

    Re: How to force an internal wire which is deep inside DUT hierachy at top level testbench using VHDL design?

    "One Cent" <> wrote in message
    news:...
    On Jul 2, 2:50 pm, backhus <> wrote:
    > On 2 Jul., 03:58, One Cent <> wrote:
    >
    > > Hi,
    > > I am interested to know how can i force an internal wire which is deep
    > > inside DUT hierachy at top level testbench using VHDL design?
    > > In verilog, i can write in this way at top level testbench as below:

    >
    > > initial
    > > begin
    > > force tb.design.memory.rx_buffer.enable_model = 1'b0;
    > > #100;
    > > force tb.design.memory.rx_buffer.enable_model = 1'b1;
    > > end

    >
    > > But how can I do this in a VHDL testbench?

    >
    > > Thanks.

    >
    > Hi,
    > if you are using Modelsim you can use the SignalSpy functions.
    > There you can access signals(wires/regs) by providing their
    > hierarchical path in the system.
    > Do a search for it in the documentation. It's all well explained.
    >
    > Have a nice simulation
    > Eilert
    >
    >Thanks Eilert!
    >This reminds me the use of init_signal_spy function in Modelsim!!


    And at the same time you might want to email your favourite Mentor support
    engineer and ask him/her to raise an ER to get VHDL2008 hierarchical references
    implemented ;-)

    Hans
    www.ht-lab.com
     
    HT-Lab, Jul 3, 2009
    #5
  6. One Cent

    NigelE Guest

    Re: How to force an internal wire which is deep inside DUT hierachyat top level testbench using VHDL design?

    On Jul 3, 8:47 am, "HT-Lab" <> wrote:
    > "One Cent" <> wrote in message
    >
    > news:...
    > On Jul 2, 2:50 pm, backhus <> wrote:
    >
    >
    >
    >
    >
    > > On 2 Jul., 03:58, One Cent <> wrote:

    >
    > > > Hi,
    > > > I am interested to know how can i force an internal wire which is deep
    > > > inside DUT hierachy at top level testbench using VHDL design?
    > > > In verilog, i can write in this way at top level testbench as below:

    >
    > > > initial
    > > > begin
    > > > force tb.design.memory.rx_buffer.enable_model = 1'b0;
    > > > #100;
    > > > force tb.design.memory.rx_buffer.enable_model = 1'b1;
    > > > end

    >
    > > > But how can I do this in a VHDL testbench?

    >
    > > > Thanks.

    >
    > > Hi,
    > > if you are using Modelsim you can use the SignalSpy functions.
    > > There you can access signals(wires/regs) by providing their
    > > hierarchical path in the system.
    > > Do a search for it in the documentation. It's all well explained.

    >
    > > Have a nice simulation
    > > Eilert

    >
    > >Thanks Eilert!
    > >This reminds me the use of init_signal_spy function in Modelsim!!

    >
    > And at the same time you might want to email your favourite Mentor support
    > engineer and ask him/her to raise an ER to get VHDL2008 hierarchical references
    > implemented ;-)
    >
    > Hanswww.ht-lab.com- Hide quoted text -
    >
    > - Show quoted text -


    It is already !

    VHDL-2008 external names was implemented in 6.5
    It works across mixed languages provided both ends are VHDL

    - Nigel
     
    NigelE, Jul 3, 2009
    #6
  7. One Cent

    HT-Lab Guest

    Re: How to force an internal wire which is deep inside DUT hierachy at top level testbench using VHDL design?

    "NigelE" <> wrote in message
    news:...
    On Jul 3, 8:47 am, "HT-Lab" <> wrote:
    > "One Cent" <> wrote in message
    >
    > news:...
    > On Jul 2, 2:50 pm, backhus <> wrote:
    >

    ...
    >
    > And at the same time you might want to email your favourite Mentor support
    > engineer and ask him/her to raise an ER to get VHDL2008 hierarchical
    > references
    > implemented ;-)
    >
    > Hanswww.ht-lab.com- Hide quoted text -
    >
    > - Show quoted text -
    >
    >It is already !
    >
    >VHDL-2008 external names was implemented in 6.5
    >It works across mixed languages provided both ends are VHDL
    >
    >- Nigel


    Hi Nigel,

    You are right, I totally missed that one when I read the vhdl2008 technote. I
    tried it out and it works great.

    local_enable <= <<signal .u1.u2.enable_s : std_logic >>;

    Thanks,
    Hans
    www.ht-lab.com
     
    HT-Lab, Jul 3, 2009
    #7
  8. One Cent

    ravik

    Joined:
    Sep 10, 2012
    Messages:
    1
    Hi,
    What is the exact format to force a signal deep inside verilog hirarchy, It's not clear from your statement:
    local_enable <= <<signal .u1.u2.enable_s : std_logic >>;

    Can you please list the exact statement ?
     
    ravik, Sep 10, 2012
    #8
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Martin Maurer
    Replies:
    2
    Views:
    2,165
    Charles Bailey
    May 21, 2004
  2. G Iveco
    Replies:
    6
    Views:
    2,597
    HT-Lab
    Jul 23, 2007
  3. kartikey
    Replies:
    0
    Views:
    1,633
    kartikey
    Dec 18, 2007
  4. JSreeniv
    Replies:
    1
    Views:
    1,199
    sri.cvcblr
    Aug 4, 2011
  5. py
    Replies:
    15
    Views:
    1,457
Loading...

Share This Page