How to force an internal wire which is deep inside DUT hierachy attop level testbench using VHDL des

O

One Cent

Hi,
I am interested to know how can i force an internal wire which is deep
inside DUT hierachy at top level testbench using VHDL design?
In verilog, i can write in this way at top level testbench as below:

initial
begin
force tb.design.memory.rx_buffer.enable_model = 1'b0;
#100;
force tb.design.memory.rx_buffer.enable_model = 1'b1;
end

But how can I do this in a VHDL testbench?

Thanks.
 
B

backhus

Hi,
I am interested to know how can i force an internal wire which is deep
inside DUT hierachy at top level testbench using VHDL design?
In verilog, i can write in this way at top level testbench as below:

initial
begin
 force tb.design.memory.rx_buffer.enable_model = 1'b0;
 #100;
  force tb.design.memory.rx_buffer.enable_model = 1'b1;
end

But how can I do this in a VHDL testbench?

Thanks.

Hi,
if you are using Modelsim you can use the SignalSpy functions.
There you can access signals(wires/regs) by providing their
hierarchical path in the system.
Do a search for it in the documentation. It's all well explained.

Have a nice simulation
Eilert
 
O

One Cent

Hi,
if you are using Modelsim you can use the SignalSpy functions.
There you can access signals(wires/regs) by providing their
hierarchical path in the system.
Do a search for it in the documentation. It's all well explained.

Have a nice simulation
  Eilert

Thanks Eilert!
This reminds me the use of init_signal_spy function in Modelsim!!
Thanks again =)
 
H

HT-Lab

Hi,
if you are using Modelsim you can use the SignalSpy functions.
There you can access signals(wires/regs) by providing their
hierarchical path in the system.
Do a search for it in the documentation. It's all well explained.

Have a nice simulation
Eilert

Thanks Eilert!
This reminds me the use of init_signal_spy function in Modelsim!!

And at the same time you might want to email your favourite Mentor support
engineer and ask him/her to raise an ER to get VHDL2008 hierarchical references
implemented ;-)

Hans
www.ht-lab.com
 
N

NigelE

And at the same time you might want to email your favourite Mentor support
engineer and ask him/her to raise an ER to get VHDL2008 hierarchical references
implemented ;-)

Hanswww.ht-lab.com- Hide quoted text -

- Show quoted text -

It is already !

VHDL-2008 external names was implemented in 6.5
It works across mixed languages provided both ends are VHDL

- Nigel
 
H

HT-Lab

...

And at the same time you might want to email your favourite Mentor support
engineer and ask him/her to raise an ER to get VHDL2008 hierarchical
references
implemented ;-)

Hanswww.ht-lab.com- Hide quoted text -

- Show quoted text -

It is already !

VHDL-2008 external names was implemented in 6.5
It works across mixed languages provided both ends are VHDL

- Nigel

Hi Nigel,

You are right, I totally missed that one when I read the vhdl2008 technote. I
tried it out and it works great.

local_enable <= <<signal .u1.u2.enable_s : std_logic >>;

Thanks,
Hans
www.ht-lab.com
 
Joined
Sep 10, 2012
Messages
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Hi,
What is the exact format to force a signal deep inside verilog hirarchy, It's not clear from your statement:
local_enable <= <<signal .u1.u2.enable_s : std_logic >>;

Can you please list the exact statement ?
 

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