How to generate a clock signal with Spartan 6?

Discussion in 'VHDL' started by kenleigh, Jan 3, 2011.

  1. kenleigh

    kenleigh

    Joined:
    Jan 3, 2011
    Messages:
    1
    I'm a noob in FPGA world.
    I recently bought a Spartan 6 dev kit (Atlys) from Digilent.
    I have read the user guide for clock management(CMT) and found that it has 4 CMT's and each CMT further has 2 DCM's and 1 PLL.
    The Atlys has a 100Mhz oscillator that clocks the Spartan.
    I want to generate a 54MHZ clock and bring it out on 1 of the I/O pins of bank 2.
    Any idea how to start with this?
     
    kenleigh, Jan 3, 2011
    #1
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