how to generate different wait time that lower than system clock cycle.

[IcYdRIP]

I have to read/write dm9000, and the dm9000 works on 25M HZ.

And according to register read/write timing of dm9000, for each
operation, we have to wait for a while to perform it.
for example, now we read register value, and following is the general
order:
1. set pin cmd high to select system address as databus.
2. when select dm9000 chip(pin aen set low), we should wait just 5ns
3. set pin ior low, wait 22ns
4. set pin ior high to read value of register to databus, and wait just
5ns(until set pin aen high)
5. set pin aen high to un-select dm9000, make bus invalid. and then
wait 80ns for next cycle.

since dm9000 works on 25M hz(40 ns).
if wait time is larger then 40ns, we can use some clock cycle to wait.
but if it's lower than 40ns, how can we do? design a multiple
frequence?
or get another external clock? such as 200M for 5ns, and 5 * 5ns for
22ns delay?

Thanks!

 

[IcYdRIP]

how to get a frequence that is X times as orginal system clock?
can anyone help me? thanks!