How to generate serial random data pattern ?

Discussion in 'VHDL' started by C T, Mar 1, 2004.

  1. C T

    C T Guest

    For the testbench, I would like to send a serial random data pattern
    (16-bit words, 10MHz clock) via a FPGA to a 512K16 RAM and then later
    on read the data back for verification.

    Please let me know what the best approach in VHDL coding to come up
    with the pattern generation and verification should be.

    Thanks.

    Calvin
    C T, Mar 1, 2004
    #1
    1. Advertising

  2. C T

    Amontec Team Guest

    C T wrote:
    > For the testbench, I would like to send a serial random data pattern
    > (16-bit words, 10MHz clock) via a FPGA to a 512K16 RAM and then later
    > on read the data back for verification.
    >
    > Please let me know what the best approach in VHDL coding to come up
    > with the pattern generation and verification should be.
    >
    > Thanks.
    >
    > Calvin


    Use pseudo-random -> a shift register and an XOR in the MSB-LSB feedback.

    Laurent www.amontec.com
    Amontec Team, Mar 2, 2004
    #2
    1. Advertising

  3. C T wrote:

    >For the testbench, I would like to send a serial random data pattern
    >(16-bit words, 10MHz clock) via a FPGA to a 512K16 RAM and then later
    >on read the data back for verification.
    >
    >Please let me know what the best approach in VHDL coding to come up
    >with the pattern generation and verification should be.
    >
    >Thanks.
    >
    >Calvin
    >


    There's a good description of linear feedback shift registers at


    http://www.newwaveinstruments.com/r...uence_linear_feedback_shift_register_lfsr.htm

    Charles B. Cameron
    Cameron, Charles B., Mar 2, 2004
    #3
  4. (C T) wrote in message news:<>...
    > For the testbench, I would like to send a serial random data pattern
    > (16-bit words, 10MHz clock) via a FPGA to a 512K16 RAM and then later
    > on read the data back for verification.
    >
    > Please let me know what the best approach in VHDL coding to come up
    > with the pattern generation and verification should be.
    >
    > Thanks.
    >
    > Calvin


    Calvin

    Ben Cohen's website has a very nice package that allows you to create
    linear-feedback shift registers (LFSRs) of many lengths. These
    generate a pseudorandom sequence that may work for you.

    http://members.aol.com/vhdlcohen/vhdl is the link.

    I have used LFSRs in testbenches and in designs. For simulations I
    have also used a random number generation procedure which produces an
    integer which I then convert to std_logic_vector or unsigned or
    whatever:

    signal Seed_s : natural := 17654; --you may pick other values for the
    seed

    procedure RandUnsigned( Size : in natural;
    signal Seed : inout natural;
    signal RandVec : out unsigned ) is

    variable Modulus : integer := ( 2 ** Size ) - 1;
    constant Multiplier_c : INTEGER := 25173;
    constant Increment_c : INTEGER := 13849;

    begin
    Seed <= ( Multiplier_c * Seed + INCREMENT_c ) mod Modulus;
    RandVec <= To_Unsigned( Seed, Size );
    end procedure RandUnsigned;

    procedure RandSLV( Size : in natural;
    signal Seed : inout natural;
    signal RandVec : out std_logic_vector )
    is

    variable Modulus : integer := ( 2 ** Size ) - 1;
    constant Multiplier_c : INTEGER := 25173;
    constant Increment_c : INTEGER := 13849;

    begin
    Seed <= ( Multiplier_c * Seed + INCREMENT_c ) mod Modulus;
    RandVec <= std_logic_vector(To_Unsigned( Seed, Size ));
    end procedure RandSLV;

    Each time you call the procedure the vector output takes on a new
    "random" value.

    Charles
    Charles M. Elias, Mar 5, 2004
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. globalrev
    Replies:
    4
    Views:
    741
    Gabriel Genellina
    Apr 20, 2008
  2. Max Kotasek
    Replies:
    4
    Views:
    965
    Max Kotasek
    Apr 9, 2010
  3. Li Chen
    Replies:
    5
    Views:
    110
    Li Chen
    Jan 16, 2008
  4. Kevin
    Replies:
    7
    Views:
    173
    Kevin
    May 17, 2011
  5. VK
    Replies:
    15
    Views:
    1,115
    Dr J R Stockton
    May 2, 2010
Loading...

Share This Page