How to generate variable labels for same component within a generate loop

Discussion in 'VHDL' started by Weng Tianxiang, Feb 12, 2006.

  1. Hi,
    I want to know how to generate variable labels for same component
    within a loop.

    The following is the code I am writing:

    component A port (
    ...
    );
    end component;

    begin
    for I in 5 to 0 generate
    xxx : A port map (
    ...
    );
    end generate;

    I don't know how to put variable I into the label xxx.

    Thank you.

    Weng
     
    Weng Tianxiang, Feb 12, 2006
    #1
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  2. On 11 Feb 2006 19:25:06 -0800, "Weng Tianxiang" <>
    wrote:

    >Hi,
    >I want to know how to generate variable labels for same component
    >within a loop.
    >
    >The following is the code I am writing:
    >
    >component A port (
    > ...
    >);
    >end component;
    >
    >begin
    > for I in 5 to 0 generate
    > xxx : A port map (
    > ...
    >);
    >end generate;
    >
    >I don't know how to put variable I into the label xxx.


    You can't modify labels that way - they are fixed at compile time.

    Note that the generated netlist *will* contain the value of "I"
    somewhere in the instance name of A, so you can still uniquely
    identify each instance. (Is that the problem you're trying to solve?)

    From memory, VHDL doesn't actually specify how the instance names are
    generated, but any practical tool will do what you want, albeit in a
    way that may vary from tool to tool.
    Verilog (the other popular HDL) does specify how the instance names
    are generated, however my experience is that the tools may not conform
    to the standard when using a generate loop (which is a relatively
    recent addition to that language).

    Regards,
    Allan
     
    Allan Herriman, Feb 12, 2006
    #2
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  3. Hi Allan,
    Surprise to learn another hole in VHDL.

    I don't have time reading full context of VHDL and hope there were some
    methods to change labels in a generate loop.

    Why cannot we add a '&' between a fixed label string and the loop
    variable like this one:

    A : for I in 5 to 0 generate
    AB&I : ModuleA port map (
    ....
    );
    end generate;

    When new lable is generated, '&' will be replaced with '_" so that
    variable lables in the above example would be generated normally: AB_5,
    AB_4, ... AB_0. This type of technique was used 50 years ago with
    assembly language.

    Currently during a generate loop with fixed labels, why doesn't a
    compiler generate an error with information: same multiple labels are
    generated!

    Thank you.

    Weng
     
    Weng Tianxiang, Feb 12, 2006
    #3
  4. On 12 Feb 2006 04:53:11 -0800, "Weng Tianxiang" <>
    wrote:

    >Hi Allan,
    >Surprise to learn another hole in VHDL.
    >
    >I don't have time reading full context of VHDL and hope there were some
    >methods to change labels in a generate loop.
    >
    >Why cannot we add a '&' between a fixed label string and the loop
    >variable like this one:
    >
    >A : for I in 5 to 0 generate
    >AB&I : ModuleA port map (
    >...
    >);
    >end generate;
    >
    >When new lable is generated, '&' will be replaced with '_" so that
    >variable lables in the above example would be generated normally: AB_5,
    >AB_4, ... AB_0. This type of technique was used 50 years ago with
    >assembly language.
    >
    >Currently during a generate loop with fixed labels, why doesn't a
    >compiler generate an error with information: same multiple labels are
    >generated!


    Because the compiler does just what you wanted: it will create unique
    labels like AB_5, AB_4, etc. It's just that the exact details are
    compiler dependent, since they are not specified in the LRM. (IIRC -
    someone please correct me if I'm wrong.)

    Regards,
    Allan
     
    Allan Herriman, Feb 12, 2006
    #4
  5. Hi Allan,
    Thank you very much for your fastest response. Are you working today on
    weekend?

    Weng
     
    Weng Tianxiang, Feb 12, 2006
    #5
  6. Weng Tianxiang

    Christophe Guest

    Hi everbody!

    Allan Herriman a écrit :

    > On 12 Feb 2006 04:53:11 -0800, "Weng Tianxiang" <>
    > wrote:
    >
    > >Hi Allan,
    > >Surprise to learn another hole in VHDL.
    > >
    > >I don't have time reading full context of VHDL and hope there were some
    > >methods to change labels in a generate loop.
    > >
    > >Why cannot we add a '&' between a fixed label string and the loop
    > >variable like this one:
    > >
    > >A : for I in 5 to 0 generate
    > >AB&I : ModuleA port map (
    > >...
    > >);
    > >end generate;
    > >
    > >When new lable is generated, '&' will be replaced with '_" so that
    > >variable lables in the above example would be generated normally: AB_5,
    > >AB_4, ... AB_0. This type of technique was used 50 years ago with
    > >assembly language.
    > >
    > >Currently during a generate loop with fixed labels, why doesn't a
    > >compiler generate an error with information: same multiple labels are
    > >generated!

    >
    > Because the compiler does just what you wanted: it will create unique
    > labels like AB_5, AB_4, etc. It's just that the exact details are
    > compiler dependent, since they are not specified in the LRM. (IIRC -
    > someone please correct me if I'm wrong.)


    Actually, the LRM (paragraph 12.4.2) specifies the elaboration of a
    generate statement.
    "[...]
    For a generate statement with a for generation scheme, elaboration
    consists of the elaboration of the discrete
    range, followed by the generation of one block statement for each value
    in the range. The block statements
    all have the following form:
    a) The label of the block statement is the same as the label of the
    generate statement.
    [..]
    "

    I don't reproduce the examples.

    A note follows:
    "NOTE-The repetition of the block labels in the case of a for
    generation scheme does not produce multiple declarations
    of the label on the generate statement. The multiple block statements
    represented by the generate statement constitute
    multiple references to the same implicitly declared label."


    Finally, I don't see exactly why a variable labels should be needed. I
    would think that the first goal is to discriminate multiple
    instanciations of your component for, let's say, different
    configurations. If so, I will quote a part (paragraph 4.2.3 GENERATE
    Usage and Configuration) of the FAQ:
    "
    The generate statement (FAQ Part 4 - B.105) is a concurrent statement
    (FAQ Part 4 - B.44) that contains other concurrent statements. Two
    forms exist: for and if generate. An example which uses both is:
    First: if i=0 generate
    Q: adder port map (A(0), B(0), Cin, Sum(0), C(0));
    end generate;
    Second: for i in 1 to 3 generate
    Q: adder port map (A(i), B(i), C(i-1), Sum(i), C(i));
    end generate;

    The components are addressed (e.g., for specification):

    First.Q, Second(1).Q, Second(2).Q, and Second(3).Q

    An external configuration specification might look like:
    for First -- First.Q
    for Q: adder use entity work.adder(architectureX);
    end for;
    end for;

    for Second(1) -- Second(1).Q
    for Q: adder use entity work.adder(architectureX);
    end for;
    end for;
    for Second(2) -- Second(2).Q
    for Q: adder use entity work.adder(architectureY);
    end for;
    end for;
    for Second(3) -- Second(3).Q
    for Q: adder use entity work.adder(architectureZ);
    end for;
    end for;
    "
    (see also LRM 1.3.1)

    Regards,
    Christophe


    >
    > Regards,
    > Allan
     
    Christophe, Feb 16, 2006
    #6
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