How to give one clock cycle in VHDL testbench?

Discussion in 'VHDL' started by Chris Waugh, Aug 14, 2013.

  1. Chris Waugh

    Chris Waugh Guest

    Can anyone please tell me how to give one clock cycle in VHDL testbench? The output result some come with one clock cycle. How can I do that?
     
    Chris Waugh, Aug 14, 2013
    #1
    1. Advertising

  2. Chris Waugh

    Chris Waugh Guest

    clk_process :process
    begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
    end process;


    -- Stimulus process
    stim_proc: process
    begin
    -- hold reset state for 100 ns.
    wait for 5 ns;
    reset <= '1';
    wait for 10 ns;
    reset <= '0';
    wait for 10 ns;
    a <= "1011011111101110000001010101111111100001101010000111111000000111100000011110101010101100111010011100101010111101011110001010111100101011000010101101011010101111010";

    -- insert stimulus here

    wait;
    end process;

    ------
    This is the testbench. I am using a 163-bit data to get a result of 163-bit output. But the whole output result must take only one clock cycle. Could you please tell me what are the modification I need here?
     
    Chris Waugh, Aug 14, 2013
    #2
    1. Advertising

  3. Chris Waugh

    Guest

    Am Mittwoch, 14. August 2013 22:30:17 UTC+2 schrieb Chris Waugh:
    > clk_process :process
    >
    > begin
    > clk <= '0';
    > wait for clk_period/2;
    > clk <= '1';
    > wait for clk_period/2;
    > end process;
    >
    >
    > -- Stimulus process
    > stim_proc: process
    > begin
    > -- hold reset state for 100 ns.
    > wait for 5 ns;
    > reset <= '1';
    > wait for 10 ns;
    > reset <= '0';
    > wait for 10 ns;
    > a <= "1011011111101110000001010101111111100001101010000111111000000111100000011110101010101100111010011100101010111101011110001010111100101011000010101101011010101111010";
    >
    > -- insert stimulus here
    > wait;
    > end process;
    > ------
    >
    > This is the testbench. I am using a 163-bit data to get a result of 163-bit output. But the whole output result must take only one clock cycle. Could you please tell me what are the modification I need here?


    Hi Chris,
    you wrote "the whole output result must take only one clock cycle", but what does that mean?
    Do you want the result to appear after one clock cycle, or do you want the result to appear for one clock cycle and then...????

    Your testbench provides a clock signal and after a short reset assigns a value for a.
    Since you did not mention anything about your DUT, noone can say what will happen at the DUTs output and when.

    The most simple synchronous device would be a register.
    This would produce an output after one clock cycle but hold it as long as the input value is stable. (Which actally means, the register output is only changing after the active clock edge, and assuming the input changes are synchronous to that too.)

    Is that what you want or something else?
    please be more specific about the problem and the projects background.

    Have a nice simulation
    Eilert
     
    , Aug 15, 2013
    #3
  4. Chris Waugh

    Chris Waugh Guest

    The whole result should come in one clock cycle only. I am taking a 163-bitinput and doing the squaring after after reduction using irreducible polynomial,I am getting a 163-bit output. So I want the result of that 163-bit in one clock duration only. How can I do that?
     
    Chris Waugh, Aug 15, 2013
    #4
  5. Chris Waugh

    Guest

    בת×ריך ×™×•× ×¨×‘×™×¢×™, 14 ב×וגוסט 2013 22:48:18 UTC+3, מ×ת Chris Waugh:
    > Can anyone please tell me how to give one clock cycle in VHDL testbench? The output result some come with one clock cycle. How can I do that?


    Here is an example:

    p_2 : process
    variable cnt : integer := 0;
    variable j : integer := 0;
    begin
    wait until clk_int'event and clk_int = '1';
    if(not fifo_read_en) then
    wait;
    end if;
    assert false report "start fifo drive" severity warning;

    for j in 1 to 31 loop
    wait until clk_int'event and clk_int = '1';
    end loop;
    reset_1 <= '1';
    for j in 1 to 9 loop
    wait until clk_int'event and clk_int = '1';
    end loop;
    reset_1 <= '0';
    for j in 1 to 4 loop
    wait until clk_int'event and clk_int = '1';
    end loop;

    mac_tx_tready_1 <= '0';
    mac_rx_tvalid_1 <= '0';
    mac_rx_tlast_1 <= '0';
    for j in 1 to 7 loop
    wait until clk_int'event and clk_int = '1';
    end loop;

    while(fifo_done = '1') loop

    http://bknpk.no-ip.biz/my_web/SDIO/vhdl_p_2_test_control.html
     
    , Aug 15, 2013
    #5
  6. Chris Waugh

    Guest

    Am Donnerstag, 15. August 2013 12:37:07 UTC+2 schrieb Chris Waugh:
    [SUGGESTED CORRECTIONS IN CAPITAL LETTERS by Eilert]
    > The whole result should come WITHin one clock cycle only. I am taking a 163-bit input and doing the squaring after after reduction using irreduciblepolynomial,I am getting a 163-bit output. So I want the result of that 163-bit AFTER one clock duration only. How can I do that?


    Hi Chris,
    so the question is not about the testbench but rather how to implement some(synthesizable) algorithm that performs its task in just one clock cycle.
    Theoretically possible, but at what cost?
    Complex algorithms fully unrolled (no feedbacks) and fully combinatorical grow big, really big! Which means there will be a high combinatorical delay causing F_max of the design to be so low that it will be barely usable. Actually it might create the result slower compared to a highly pipelined design running for a number of clock cycles at a high clock frequency.

    You are talking about some squaring (x^2=x*x) which means a multiplication and also about a irreducible polinom which hints that you are working with Galois fields (e.g. for some cryptographic design). While the GF-Multiplication might become quite simple, the polinomal reduction (which is some modulo function in the end) can become more difficult.
    If there is any hope for your approach it might be in the numerical properties of your GF-sqaring function.

    You will find many such threads in the forums here and at comp.arch.fpga.
    And all get a similar answer like the one above.
    So spend some thoughts about the requirements you have for the design and if there's some more reasonable approach.

    Have a nice synthesis
    Eilert
     
    , Aug 16, 2013
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Replies:
    4
    Views:
    759
    Peter Alfke
    Apr 27, 2006
  2. Drew
    Replies:
    0
    Views:
    482
  3. Amit
    Replies:
    9
    Views:
    2,718
    Nicolas Matringe
    May 8, 2007
  4. varunvlsi

    in one clock cycle

    varunvlsi, Oct 5, 2007, in forum: VHDL
    Replies:
    1
    Views:
    537
    scottcarl
    Oct 11, 2007
  5. Replies:
    5
    Views:
    787
Loading...

Share This Page