How to handle floating inputs in a device?

[Calvin]

I am doing HDL coding for a dual-purpose FPGA/ASIC: The same FPGA/ASIC
will be used on two different board configurations.

The boards have been completed and in one board configuration, I now
have some floating inputs, i.e. FPGA/ASIC physical pins (for inputs)
are not connected/driven.

Can I handle floating inputs with HDL coding ?

Thanks,

Calvin

 

[Zara]

I am doing HDL coding for a dual-purpose FPGA/ASIC: The same FPGA/ASIC
will be used on two different board configurations.

The boards have been completed and in one board configuration, I now
have some floating inputs, i.e. FPGA/ASIC physical pins (for inputs)
are not connected/driven.

Can I handle floating inputs with HDL coding ?

Thanks,

Calvin

The best way is to implement PULL-UP or PULL-DOWN, whichever is better,
because 'Z' is an output state, not a detectable input state

 

[Calvin]

If I have a port 'xyz' defined as a std_logic input (its physical pin
is not connected), how can I assign a pullup 'H' or a pulldown 'L' to
that port in HDL ?

modelsim vcom results in an error, saying "Can not drive input signal
'xyz' "!

I do not have to worry about this port if it is a bi-directional one,
do I ?

Thanks,

Calvin

 

[Zara]

If I have a port 'xyz' defined as a std_logic input (its physical pin
is not connected), how can I assign a pullup 'H' or a pulldown 'L' to
that port in HDL ?

modelsim vcom results in an error, saying "Can not drive input signal
'xyz' "!

I do not have to worry about this port if it is a bi-directional one,
do I ?

Thanks,

Calvin

The way to simulte it is , if it is a PULL-UP, assining to it a '1' if
driven high or floating, and a '0' if driven low.

Bi-directional ports are tricky, I would not recommend them except when
dealing with external pins in synthesis. For simulation it is best to
separate inputs from outputs and express the behaviour of the ports in
the testbench

 

[Calvin]

Sorry that I did not make my question clear!

In my FPGA/ASIC, if I have an entity defined as follows:

entity design_top is
port (
...
xyz : in std_logic;
...
);
end design_top;

If the FPGA/ASIC physical pin for xyz input is NOT CONNECTED (left
floating), how can I take care of this floating input port in my HDL
coding ?

I can not assign a value to this port by doing

xyz <= '0';

or any other values since modelsim vcom results in an error, saying
"Can not drive input signal 'xyz' "!

Thanks,

Calvin

 

[Mike Treseler]

If the FPGA/ASIC physical pin for xyz input is NOT CONNECTED (left
floating), how can I take care of this floating input port in my HDL
coding ?

You could add pulldown resistors to the board
or use device specific attributes if the FPGA
has programmable terminations.

You could use different HDL configurations
for each board.

You could add a mode input and extra logic
to the fpga so that it knows what board is
attached and provides the correct
input muxing for every case.

-- Mike Treseler

 

[Calvin]

Hi Mike,

I like your ideas. Since the board is already done, they do not want to
add pulldown resistors to unconnected input pins!

Based on your third option, can I do something like the following:

entity design_top is
port (
...
xyz : in std_logic;
config_select : in std_logic;
... );

signal xyz_internal : std_logic;
....
with config_select select
xyz_internal <= xyz when '1', -- input pin connected
'0' when others; -- input pin
unconnected

....



Thanks,

Calvin

 

[Peter]

If your FPGA is in-system reprogrammable you can use different code for
each application. If you dont use an input, it will be set to output or
tristate depending on your tools.
If you have an OTP FPGA or ASIC, you are in trouble. Unused inputs
shall be connected to a valid logic level to prevent excessive current
drain. There I cant see any alternative to a board redesign.

/Peter

 

[Peter]

If your FPGA is in-system reprogrammable you can use different code for
each application. If you dont use an input, it will be set to output or
tristate depending on your tools.
If you have an OTP FPGA or ASIC, you are in trouble. Unused inputs
shall be connected to a valid logic level to prevent excessive current
drain. There I cant see any alternative to a board redesign.

/Peter

 

[jens]

Check your FPGA/ASIC documentation to see if you can assign a weak
pull-up to your input (I just checked the Altera Stratix handbook and
you can, I think you can with Xilinx Virtex too). Then you can avoid
both excessive power consumption and a board re-design.