How to handle varied length of output signal

Discussion in 'VHDL' started by systolic, Oct 21, 2004.

  1. systolic

    systolic Guest

    I am doing compression algorithm using VHDL. I need to output different
    length of codes according to different intermediate computation results.
    In this way, I compress the original information.

    For example, if intermediate computation result is less than certain
    threshold, I will output 5 bits, but if it is greater than the
    threshold, I only need to output 3 bits.

    How could I handle the definition of the output signal?
    I thougth about using 2 'Z's to concatenate with 3 bits. It didn't work,
    turned my output to "ZX". Sad

    Any suggestions or hints? TIA
     
    systolic, Oct 21, 2004
    #1
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  2. systolic

    rickman Guest

    systolic wrote:
    >
    > I am doing compression algorithm using VHDL. I need to output different
    > length of codes according to different intermediate computation results.
    > In this way, I compress the original information.
    >
    > For example, if intermediate computation result is less than certain
    > threshold, I will output 5 bits, but if it is greater than the
    > threshold, I only need to output 3 bits.
    >
    > How could I handle the definition of the output signal?
    > I thougth about using 2 'Z's to concatenate with 3 bits. It didn't work,
    > turned my output to "ZX". Sad
    >
    > Any suggestions or hints? TIA


    I am curios about how you will use this result with dynamically changing
    size. You can compress the data, but a compression algorithm can't
    change the number of wires in hardware. You still need enough wires to
    carry the maximum width signal.

    Think about what you are doing in terms of the hardware you will be
    building. VHDL is not a programming language, it is a Hardware
    Description Language V*HDL*.

    Hint: just set the unused bits to zeros...

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Oct 21, 2004
    #2
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  3. On Thu, 2004-10-21 at 01:50 -0500, systolic wrote:
    > I am doing compression algorithm using VHDL. I need to output different
    > length of codes according to different intermediate computation results.
    > In this way, I compress the original information.
    >
    > For example, if intermediate computation result is less than certain
    > threshold, I will output 5 bits, but if it is greater than the
    > threshold, I only need to output 3 bits.
    >
    > How could I handle the definition of the output signal?
    > I thougth about using 2 'Z's to concatenate with 3 bits. It didn't work,
    > turned my output to "ZX". Sad
    >
    > Any suggestions or hints? TIA
    >


    It kind of depends on how you want to output transmitted. If you are
    transmitting the results one at a time and they are self delimitting,
    set the other bits to zero or one. Otherwise transmit an additional
    signal of 3 or 4 bits indicating how long the result is in bits.

    If you want to pack the results into a fixed size packet (eg byte) then
    use a shift register to accumulate the results. When then is more than
    a byte worth, you shift a byte out. This is kind of like a fifo.
     
    Prasanth Kumar, Oct 21, 2004
    #3
  4. systolic

    systolic Guest

    Thx, guys,
    So, I need to either use two buses with an extra flag bit. Or just add
    padding '0' or '1'.
    I will take the first choice since I need to have pure compressed code.
     
    systolic, Oct 21, 2004
    #4
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