How to implement a counter

Discussion in 'VHDL' started by jcafaro10, Sep 24, 2009.

  1. jcafaro10

    jcafaro10

    Joined:
    Nov 12, 2007
    Messages:
    3
    I'm trying to implement a counter that counts down from 64.

    Here's my setup, I have a component that I designed that takes a serial input and stores it in memory. It can store 1 byte at a time. I have an 8 byte shift register that feeds into this component because I need to check for an 8 byte sequence before I start feeding things into memory. I have that part working.

    I have a valid signal that is asserted at some point during my input, and stays asserted until my input is no longer valid. I have a falling edge detector for it so I get a pulse when my valid signal goes from 1 to 0.

    What I need is a counter that counts 64 bits starting on that falling edge. I need this because I need to make sure that I write all of the bits that are in the 8 byte shift register to memory. I can't figure out how to make the counter count.

    Here's my code so far. I'm not very good with vhdl, but hopefully my comments should help explain my ideas:
    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all; 
    --THIS CLASS IS RESPONSIBLE FOR READING IN FRAMES AND STORING THEM
    entity framehandler is
    	port
    	(
    		clk,reset: in std_logic;
    		input: in std_logic; -- my input stream
    		valid: in std_logic; -- valid signal is high at some point during input stream and low at the end of the input stream
    		output: out std_logic;
    		writing: out std_logic_vector(7 downto 0); -- test signal to see whats being written to memory
    		reading: out std_logic_vector(7 downto 0); -- test signal to see what's being read from memory
    		writeout: out std_logic;--test signal to see when writeEN is high
    		readout: out std_logic;--test signal to see when readEN is high
    		startout: out std_logic;--test signal to see when start is high
    		addressout: out std_logic_vector(9 downto 0);--test signal to see the address
    		countdownout: out integer range 0 to 63 --test signal to see the countdown
    	);
    end framehandler;
    
    architecture structure of framehandler is
    	signal writeEN: std_logic; --write 8 bits to memory
    	signal readEN: std_logic; --read 8 bits from memory
    	signal address: std_logic_vector(9 downto 0);
    	signal temp: std_logic; -- for falling edge detector
    	signal valid_fe: boolean; -- detected a falling edge
    	signal preamble_buffer: std_logic_vector(63 downto 0); --hold the preamble to check
    	signal store: std_logic; -- pass output of preamble_buffer to input of memory
    	signal start: std_logic; -- start writing stuff to memory
    	signal counter: integer range 0 to 7; -- we want to write 8 bits at a time so this counter makes sure we have 8 new bits to write
    	signal countdown: integer range 0 to 63; -- this is the counter I'm trying to implement
    	
    	component rshift8byte is
    	PORT
    	(
    		clock		: IN STD_LOGIC ;
    		sclr		: IN STD_LOGIC ;
    		shiftin		: IN STD_LOGIC ;
    		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
    		shiftout		: OUT STD_LOGIC 
    	);
    	END component;
    
    	component framestore is
    	port
    	(
    		clk,reset : in std_logic;
    		input: in std_logic;
    		writeEN : in std_logic;
    		readEN: in std_logic;
    		rwAddress: in std_logic_vector(9 downto 0);
    		output : out std_logic;
    		writing : out std_logic_vector(7 downto 0); --test signal
    		reading : out std_logic_vector(7 downto 0) --test signal
    	);
    	end component;
    	
    begin
    	process(clk,reset)
    	begin
    	if(reset = '1') then
    		readEN <= '0';
    		address <= "0000000000";
    		temp <= '0';
    		start <= '0';
    	elsif(clk'event and clk='1') then
    		temp <= valid; -- for my falling edge detector
    		if(start='1') then
    		--if(start='1' or countdown > 0) then (this is the part I can't get to work)
    			counter <= counter + 1;
    		end if;
    		if(preamble_buffer = "1101010101010101010101010101010101010101010101010101010101010101") then
    			start <= '1';
    		end if;
    		if(counter = 7) then
    			address <= address + '1'; --write to another address
    		end if;
    	end if;
    	end process;
    
    	buffering: rshift8byte port map(clk,reset,input,preamble_buffer,store);
    	storeage: framestore port map(clk,reset,store,writeEN,readEN,address,output,writing,reading);
    	
    valid_fe <= temp='1' and valid='0'; -- falling edge detector
    --countdown <= countdown + 1 when valid_fe or countdown > 0 else 0; (can't get this to work, basically I only want to start counting when the falling edge occurs, and I want to stop counting when I wrap around back to 0)
    writeEN <= '1' when start <= '1' and counter = 7 else '0';
    --writeEN <= '1' when (start <= '1' or countdown > 0) and counter = 7 else '0';
    writeout<=writeEN;
    readout<=readEN;
    startout<=start;
    addressout <= address;
    --countdownout <= countdown;
    end structure;
    
     
    jcafaro10, Sep 24, 2009
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Tom Vande Stouwe MCSD.net

    Re: How to implement counter?

    Tom Vande Stouwe MCSD.net, Jul 24, 2003, in forum: ASP .Net
    Replies:
    0
    Views:
    405
    Tom Vande Stouwe MCSD.net
    Jul 24, 2003
  2. Tu-Thach

    How to implement counter?

    Tu-Thach, Jul 24, 2003, in forum: ASP .Net
    Replies:
    0
    Views:
    389
    Tu-Thach
    Jul 24, 2003
  3. The Eeediot
    Replies:
    3
    Views:
    2,305
    =?Utf-8?B?UnVsaW4gSG9uZw==?=
    Dec 22, 2004
  4. Mario Krsnic

    beginer in ASP - how to implement counter

    Mario Krsnic, Jun 18, 2006, in forum: ASP .Net
    Replies:
    5
    Views:
    2,548
    Juan T. Llibre
    Jun 18, 2006
  5. George2
    Replies:
    1
    Views:
    852
    Alf P. Steinbach
    Jan 31, 2008
Loading...

Share This Page