how to implement variable ports with variable width?

[weijun]

I need to implement a module that has variable number of ports and the
width of the port is also variable (but same for all ports). Can
someone suggest a way to do that?
Thanks a lot!

 

[Jim Lewis]

weijun,
Use a set of subprograms with unconstrained arrays.

Regards,
Jim

I need to implement a module that has variable number of ports and the
width of the port is also variable (but same for all ports). Can
someone suggest a way to do that?
Thanks a lot!

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Robert Reutemann]

I need to implement a module that has variable number of ports and the
width of the port is also variable (but same for all ports). Can
someone suggest a way to do that?
Thanks a lot!

If you really need a port, there are (at least) two possibilities:

- use a configuration package where you define an array of arrays
of the proper size. The sizes are best declared as constants
in that package, so they can be accessed by code across entities
(by including the package).

- use a one-dimensional port, e.g. std_logic_vector(M*N-1 downto 0)
for the port. Within the modules you can of course again use
two-dimensional arrays and just assign accordingly. In this case,
M and N can be generics.

I would strongly suggest the second solution, since complex data
structures on ports lead to problems in synthesis/netlists.

The first solution may be OK if the module is only ever used
internally and you never need to work with a (often verilog)
netlist of that module.

Robert

 

[Mike Treseler]

I need to implement a module that has variable number of ports and the
width of the port is also variable (but same for all ports). Can
someone suggest a way to do that?

Complex data structures are best left to process variables.
Ports should hide internal registers whenever possible.

-- Mike Treseler

 

[Amal]

Nowadays, most synthesis tools support records. You can define your
ports as record types in a package, one for inputs and one for outputs.
Until the next VHDL-200x defines direction for each record element as
in SystemVerilog interfaces, you can use this method.

-- Amal