how to in INSTANTIATING large number of components?

G

Guest

Dear all,

Could any one telll me how to change 64 INSTANTIATION (MEMxx) below
into
a for loop?

Yick

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

entity viterbi is
generic (VITERBI_Q, VITERBI_N, VITERBI_L, VITERBI_NUM_STATES:
integer);
port ( clk : in std_logic;
reset : in std_logic;
receive_symbol0 : in std_logic_vector((VITERBI_Q-1) downto
0);
receive_symbol1 : in std_logic_vector((VITERBI_Q-1) downto
0);
inputting : in std_logic;
input_ready : out std_logic;
symbol : out std_logic
);
end viterbi;

architecture behaviour of viterbi is

constant PATH_METRICE_NUM_BITS : integer := 10;

component butterfly_ACS is
generic (PATH_METRICE_NUM_BITS, Q, ENCODER_N:integer);
port (
clk : in std_logic;
PM0_IN : in signed((PATH_METRICE_NUM_BITS-1) downto 0);
PM1_IN : in signed((PATH_METRICE_NUM_BITS-1) downto 0);
SYM0 : in signed((Q-1) downto 0);
SYM1 : in signed((Q-1) downto 0);
CMD : in std_logic_vector(1 downto 0);
PM0_OUT: out signed((PATH_METRICE_NUM_BITS-1) downto 0);
TBR0 : out std_logic;
PM1_OUT: out signed((PATH_METRICE_NUM_BITS-1) downto 0);
TBR0 : out std_logic;
PM1_OUT: out signed((PATH_METRICE_NUM_BITS-1) downto 0);
TBR1 : out std_logic;
XXX_ZERO_TO_ZERO_XXX_INPUT_0: in std_logic_vector((ENCODER_N-1)
downto 0);
XXX_ZERO_TO_ONE_XXX_INPUT_1 : in std_logic_vector((ENCODER_N-1)
downto 0);
XXX_ONE_TO_ZERO_XXX_INPUT_0 : in std_logic_vector((ENCODER_N-1)
downto 0);
XXX_ONE_TO_ONE_XXX_INPUT_1 : in std_logic_vector((ENCODER_N-1)
downto 0)
);
end component;

component memory_unit is
generic (NUM_BITS: integer := PATH_METRICE_NUM_BITS);
port (
clk : in std_logic;
out_sel : in std_logic;
reset : in std_logic;
input : in std_logic_vector((NUM_BITS-1) downto 0);
output : out std_logic_vector((NUM_BITS-1) downto 0)
);
end component;

component stack is
generic (STACK_SIZE: integer);
port (
clk : in std_logic;
push_pop : in std_logic;
input : in std_logic;
output : out std_logic
);
end component;

type state_t is (
S_READY
);

type PM_TYPE is array (0 to (VITERBI_NUM_STATES-1))
of std_logic_vector((PATH_METRICE_NUM_BITS-1) downto 0);
signal PM_IN, PM_OUT: PM_TYPE;

signal cur_state: state_t;
signal mem_clk: std_logic;
signal mem_sel: std_logic;

begin
process(reset, CLK)
begin
if (RESET='1') then -- asynchronous reset
elsif (CLK'event and CLK='1') then
end if;
end process;

MEM00: memory_unit port map (mem_clk, mem_sel, reset, PM_IN( 0),
PM_OUT( 0));
MEM01: memory_unit port map (mem_clk, mem_sel, reset, PM_IN( 1),
PM_OUT( 1));
MEM02: memory_unit port map (mem_clk, mem_sel, reset, PM_IN( 2),
PM_OUT( 2));
MEM03: memory_unit port map (mem_clk, mem_sel, reset, PM_IN( 3),
PM_OUT( 3));
MEM04: memory_unit port map (mem_clk, mem_sel, reset, PM_IN( 4),
PM_OUT( 4));
MEM05: memory_unit port map (mem_clk, mem_sel, reset, PM_IN( 5),
PM_OUT( 5));
MEM06: memory_unit port map (mem_clk, mem_sel, reset, PM_IN( 6),
PM_OUT( 6));
MEM07: memory_unit port map (mem_clk, mem_sel, reset, PM_IN( 7),
PM_OUT( 7));
MEM08: memory_unit port map (mem_clk, mem_sel, reset, PM_IN( 8),
PM_OUT( 8));
MEM09: memory_unit port map (mem_clk, mem_sel, reset, PM_IN( 9),
PM_OUT( 9));
MEM10: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(10),
PM_OUT(10));
MEM31: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(31),
PM_OUT(31));
MEM32: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(32),
PM_OUT(32));
MEM33: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(33),
PM_OUT(33));
MEM34: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(34),
PM_OUT(34));
MEM35: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(35),
PM_OUT(35));
MEM36: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(36),
PM_OUT(36));
MEM37: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(37),
PM_OUT(37));
MEM38: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(38),
PM_OUT(38));
MEM39: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(39),
PM_OUT(39));
MEM40: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(40),
PM_OUT(40));
MEM41: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(41),
PM_OUT(41));
MEM42: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(42),
PM_OUT(42));
MEM43: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(43),
PM_OUT(43));
MEM44: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(44),
PM_OUT(44));
MEM45: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(45),
PM_OUT(45));
MEM46: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(46),
PM_OUT(46));
MEM47: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(47),
PM_OUT(47));
MEM48: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(48),
PM_OUT(48));
MEM49: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(49),
PM_OUT(49));
MEM50: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(50),
PM_OUT(50));
MEM51: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(51),
PM_OUT(51));
MEM52: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(52),
PM_OUT(52));
MEM53: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(53),
PM_OUT(53));
MEM54: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(54),
PM_OUT(54));
MEM55: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(55),
PM_OUT(55));
MEM56: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(56),
PM_OUT(56));
MEM57: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(57),
PM_OUT(57));
MEM58: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(58),
PM_OUT(58));
MEM59: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(59),
PM_OUT(59));
MEM60: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(60),
PM_OUT(60));
MEM61: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(61),
PM_OUT(61));
MEM62: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(62),
PM_OUT(62));
MEM63: memory_unit port map (mem_clk, mem_sel, reset, PM_IN(63),
PM_OUT(63));
end behaviour;
 
T

Thomas Reinemann

nospam said:
Dear all,

Could any one telll me how to change 64 INSTANTIATION (MEMxx) below
into
a for loop?

Yick

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

entity viterbi is
generic (VITERBI_N, VITERBI_L, VITERBI_NUM_STATES:
integer);
port ( clk : in std_logic;
reset : in std_logic;
receive_symbol0 : in std_logic_vector;
receive_symbol1 : in std_logic_vector
inputting : in std_logic;
input_ready : out std_logic;
symbol : out std_logic
);
end viterbi;

architecture behaviour of viterbi is

constant PATH_METRICE_NUM_BITS : integer := 10;
constant VITERBI_Q : integer := receive_symbol0'length;
component butterfly_ACS is
generic (PATH_METRICE_NUM_BITS, Q, ENCODER_N:integer);
port (
clk : in std_logic;
PM0_IN : in signed((PATH_METRICE_NUM_BITS-1) downto 0);
PM1_IN : in signed((PATH_METRICE_NUM_BITS-1) downto 0);
SYM0 : in signed((Q-1) downto 0);
SYM1 : in signed((Q-1) downto 0);
CMD : in std_logic_vector(1 downto 0);
PM0_OUT: out signed((PATH_METRICE_NUM_BITS-1) downto 0);
TBR0 : out std_logic;
PM1_OUT: out signed((PATH_METRICE_NUM_BITS-1) downto 0);
TBR0 : out std_logic;
PM1_OUT: out signed((PATH_METRICE_NUM_BITS-1) downto 0);
TBR1 : out std_logic;
XXX_ZERO_TO_ZERO_XXX_INPUT_0: in std_logic_vector((ENCODER_N-1)
downto 0);
XXX_ZERO_TO_ONE_XXX_INPUT_1 : in std_logic_vector((ENCODER_N-1)
downto 0);
XXX_ONE_TO_ZERO_XXX_INPUT_0 : in std_logic_vector((ENCODER_N-1)
downto 0);
XXX_ONE_TO_ONE_XXX_INPUT_1 : in std_logic_vector((ENCODER_N-1)
downto 0)
);
end component;

component memory_unit is
generic (NUM_BITS: integer := PATH_METRICE_NUM_BITS);
port (
clk : in std_logic;
out_sel : in std_logic;
reset : in std_logic;
input : in std_logic_vector((NUM_BITS-1) downto 0);
output : out std_logic_vector((NUM_BITS-1) downto 0)
);
end component;

component stack is
generic (STACK_SIZE: integer);
port (
clk : in std_logic;
push_pop : in std_logic;
input : in std_logic;
output : out std_logic
);
end component;

type state_t is (
S_READY
);

type PM_TYPE is array (0 to (VITERBI_NUM_STATES-1))
of std_logic_vector((PATH_METRICE_NUM_BITS-1) downto 0);
signal PM_IN, PM_OUT: PM_TYPE;

signal cur_state: state_t;
signal mem_clk: std_logic;
signal mem_sel: std_logic;

begin
process(reset, CLK)
begin
if (RESET='1') then -- asynchronous reset
elsif (CLK'event and CLK='1') then
end if;
end process;
memo: for i in 0 to PM_IN'length - 1 generate
memory_unit port map (mem_clk, mem_sel, reset, PM_IN(i), PM_OUT(i));
end generate memo;
 
W

Weng Tianxiang

Thomas,
I have the same question as Neo does.

Can you explain the meaning of the following statement:
constant VITERBI_Q : integer := receive_symbol0'length;

The essential of the question is it wants a variable unit name that can
be changed in a 'generate' loop.

Is there any formal semantics or reference to the problem resolution.

Your method doesn't give any relationships with the memory_unit name.

I have a book named "HDL Chip Design" and it doesn't have the semantics
about variable unit name in 'generate' loop.

Weng
 
T

Thomas Reinemann

Weng said:
Thomas,
I have the same question as Neo does.

Can you explain the meaning of the following statement:
constant VITERBI_Q : integer := receive_symbol0'length;
The original post has an additional generic "VITERBI_Q". Since you can
obtain this information from the signal "receive_symbol0", it isn't
really needed on this place. The entity gets simpler and more flexible
by this.
The essential of the question is it wants a variable unit name that can
be changed in a 'generate' loop.

Is there any formal semantics or reference to the problem resolution.

Your method doesn't give any relationships with the memory_unit name.

I have a book named "HDL Chip Design" and it doesn't have the semantics
about variable unit name in 'generate' loop.

Generate statements are evaluated during elaboration. During this stage
only constant values are assumed.
Usually I prefer this range specification. Since the range is linked
obviously to the signal PM_IN. I could use VITERBI_NUM_STATES-1, but
without knowledge of PM_TYPE you couldn't relate it to PM_IN. In fact I
didn't regard PM_IN's type as I wrote the answer. May be it will not
work in this case, since PM_TYPE is an array.

Bye Tom
 

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