P
Pasacco
dear
I am trying to initialize 1024 numbers (each 32 bit) in one entity,
using XIilinx BRAM.
In VHDL, BRAM (RAMB16_S18, 1024-deep, 16-wide) have been declared and
instantiated as shown below.
Problem is that I do not know how to initialize (for example, using
'generic' and 'INIT_XX') BRAM, in case there is ONE declaration and TWO
instantiations of identical component.
Does someone have experience?
Thankyou in advance, regards
------------------------------------------------------------------------------------------------------
-- declare BRAM RAMB16_S18
component RAMB16_S18
port (
DO: out STD_LOGIC_VECTOR (15 downto 0;
DOP: out STD_LOGIC_VECTOR (1 downto 0);
ADDR: in STD_LOGIC_VECTOR (9 downto 0);
CLK: in STD_ULOGIC;
DI: in STD_LOGIC_VECTOR (15 downto 0);
DIP: in STD_LOGIC_VECTOR (1 downto 0);
EN: in STD_ULOGIC;
SSR: in STD_ULOGIC;
WE: in STD_ULOGIC);
end component;
..
..
--Instantiation of BRAM 1
RAM00 : RAMB16_S18
port map(
do => doMem(15 downto 0),
dop => dop1,
addr => addrMem,
clk => clock,
di => diMem(15 downto 0),
dip => dip1,
en => enMem,
ssr => reset,
we => weMem);
--Instantiation of BRAM 2
RAM01 : RAMB16_S18
port map(
do => doMem(31 downto 16),
dop => dop2,
addr => addrMem,
clk => clock,
di => diMem(31 downto 16),
dip => dip2,
en => enMem,
ssr => reset,
we => weMem);
---------------------------------------------------------------------------------------------
I am trying to initialize 1024 numbers (each 32 bit) in one entity,
using XIilinx BRAM.
In VHDL, BRAM (RAMB16_S18, 1024-deep, 16-wide) have been declared and
instantiated as shown below.
Problem is that I do not know how to initialize (for example, using
'generic' and 'INIT_XX') BRAM, in case there is ONE declaration and TWO
instantiations of identical component.
Does someone have experience?
Thankyou in advance, regards
------------------------------------------------------------------------------------------------------
-- declare BRAM RAMB16_S18
component RAMB16_S18
port (
DO: out STD_LOGIC_VECTOR (15 downto 0;
DOP: out STD_LOGIC_VECTOR (1 downto 0);
ADDR: in STD_LOGIC_VECTOR (9 downto 0);
CLK: in STD_ULOGIC;
DI: in STD_LOGIC_VECTOR (15 downto 0);
DIP: in STD_LOGIC_VECTOR (1 downto 0);
EN: in STD_ULOGIC;
SSR: in STD_ULOGIC;
WE: in STD_ULOGIC);
end component;
..
..
--Instantiation of BRAM 1
RAM00 : RAMB16_S18
port map(
do => doMem(15 downto 0),
dop => dop1,
addr => addrMem,
clk => clock,
di => diMem(15 downto 0),
dip => dip1,
en => enMem,
ssr => reset,
we => weMem);
--Instantiation of BRAM 2
RAM01 : RAMB16_S18
port map(
do => doMem(31 downto 16),
dop => dop2,
addr => addrMem,
clk => clock,
di => diMem(31 downto 16),
dip => dip2,
en => enMem,
ssr => reset,
we => weMem);
---------------------------------------------------------------------------------------------