How to instantiate identical components by for loop or generate in VHDL?

Discussion in 'VHDL' started by boku, Apr 27, 2005.

  1. boku

    boku Guest

    Dear all,
    I'm trying to use For-loop or generate to instantiate RAM
    components but am stuck. I don't know how to assign each instance name
    so I can reference each individual component. Or generate statement
    can achieve this? Looking forward to ur answer. Thanks a lot!~

    --------------------------------------------
    for n in SWMMBSIZE_IN_ROW-1 downto 0 loop
    swmsram(n): mbbankinswm
    port map(
    address => std_logic_vector(addr),
    datain => din,
    write => write,
    dataout => dout,
    clk => clk
    );
    end loop;
     
    boku, Apr 27, 2005
    #1
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  2. boku

    avishay Guest

    Hi
    This is the code you need:

    for n in SWMMBSIZE_IN_ROW-1 downto 0 generate
    swmsram: mbbankinswm
    port map(
    address => std_logic_vector(addr),
    datain => din,
    write => write,
    dataout => dout(n), -- <== Note this!
    clk => clk
    );
    end loop;

    Notes:
    1. You should use the GENERATE statement. This is a concurrent
    statement (not within a process).
    2. At elaboration time, a numbered sufix is appended to each component
    label. I
    don't know if this suffix is standart among all
    simulators/synthesizers, but this is not a problem unless you need to
    refer a component's label.
    3. Some port mappings (at least outputs, usually) must be dependent on
    the loop variable, or else all your generated components will be
    connected in parallel.

    Hope it helps,
    Avishay

    boku wrote:
    > Dear all,
    > I'm trying to use For-loop or generate to instantiate RAM
    > components but am stuck. I don't know how to assign each instance

    name
    > so I can reference each individual component. Or generate statement
    > can achieve this? Looking forward to ur answer. Thanks a lot!~
    >
    > --------------------------------------------
    > for n in SWMMBSIZE_IN_ROW-1 downto 0 loop
    > swmsram(n): mbbankinswm
    > port map(
    > address => std_logic_vector(addr),
    > datain => din,
    > write => write,
    > dataout => dout,
    > clk => clk
    > );
    > end loop;
     
    avishay, Apr 27, 2005
    #2
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  3. If you need the component label to (for example) apply an attribute,
    you put the attribute inside the lpp. Thus:

    for n in RANGE generate
    -- attributes here
    begin -- Note we now need a "begin"
    -- as before

    "avishay" <> wrote:

    :Hi
    :This is the code you need:
    :
    :for n in SWMMBSIZE_IN_ROW-1 downto 0 generate
    : swmsram: mbbankinswm
    : port map(
    : address => std_logic_vector(addr),
    : datain => din,
    : write => write,
    : dataout => dout(n), -- <== Note this!
    : clk => clk
    : );
    :end loop;
    :
    :Notes:
    :1. You should use the GENERATE statement. This is a concurrent
    :statement (not within a process).
    :2. At elaboration time, a numbered sufix is appended to each component
    :label. I
    :don't know if this suffix is standart among all
    :simulators/synthesizers, but this is not a problem unless you need to
    :refer a component's label.
    :3. Some port mappings (at least outputs, usually) must be dependent on
    :the loop variable, or else all your generated components will be
    :connected in parallel.
    :
    :Hope it helps,
    :Avishay
    :
    :boku wrote:
    :> Dear all,
    :> I'm trying to use For-loop or generate to instantiate RAM
    :> components but am stuck. I don't know how to assign each instance
    :name
    :> so I can reference each individual component. Or generate statement
    :> can achieve this? Looking forward to ur answer. Thanks a lot!~
    :>
    :> --------------------------------------------
    :> for n in SWMMBSIZE_IN_ROW-1 downto 0 loop
    :> swmsram(n): mbbankinswm
    :> port map(
    :> address => std_logic_vector(addr),
    :> datain => din,
    :> write => write,
    :> dataout => dout,
    :> clk => clk
    :> );
    :> end loop;
     
    David R Brooks, Apr 28, 2005
    #3
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