How to make Clock Divider

Discussion in 'VHDL' started by dadili, Dec 10, 2011.

  1. dadili

    dadili

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    I have to make clock divider from 50MHz to 2.5 Hz. I have no idea how to do it. can someone help me, write the code or explain to me.
    dadili, Dec 10, 2011
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  2. dadili

    jeppe

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    Try something like this:

    Code:
    process( Clk_50MHz)
       variable Count20: integer range 0 to 20000000;
    begin
        if Rising_edge( Clk_50MHz) then
             if Count20>1 then
                 Clk_2p5Hz <= '0';
                 Count20 := Count20-1; 
            else
                 Clk_2p5Hz <= '1';     
                 Count20 := 20000000;
            end if; 
       end if;
    end process;
    Last edited: Dec 11, 2011
    jeppe, Dec 11, 2011
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  3. dadili

    jeppe

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    The 2p5Hz will however be short (say 20 nanosec) but its possible to make it wider
    (try this yourself)
    jeppe, Dec 11, 2011
    #3
  4. dadili

    dadili

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    can you explain me this part

    why this range to 20000000

    what is it working here?

    dadili, Dec 11, 2011
    #4
  5. dadili

    jeppe

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    50MHz = 50.000.000 Hz
    50.000.000 Hz / 2,5Hz = 20.000.000 = 20000000
    Hence must you count 20 million pulses of the 50MHz frequiency to make one
    pulse of the 2,5 Hz signal.

    This answer both questions I believe.
    jeppe, Dec 11, 2011
    #5
  6. dadili

    dadili

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    can I do it like this?

    Code:
    entity clock is
    port
    (
           clk: in std_logic;
           clok_o: buffer std_logic
    );
    end clock;
    
    architecture Desc of clock is
    begin
    process(clk)
          variable count: integer range 0 to 20000000;
          begin
                 if (clk'event and clk='1') then
                 count:=count+1;
                 if(count>=20000000) then
                      clk_o<=not clk_o;
                      count:=0;
    end if;
    end if;
    end process;
    end Desc;
    
    Last edited: Dec 11, 2011
    dadili, Dec 11, 2011
    #6
  7. dadili

    jeppe

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    Yes :)

    But in this case should you change 20000000 to 10000000
    then clk_o will get 50% as '0' and 50% as '1' of the 1/2.5 time period
    jeppe, Dec 11, 2011
    #7
  8. dadili

    dadili

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    Dec 10, 2011
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    Thanks for your help, but I dont understand why 10000000?
    dadili, Dec 11, 2011
    #8
  9. dadili

    jeppe

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    In my first example did you get:
    19.999.999 clock periodes with clk_o = '0'
    and
    1 clock period with clk_o = '1'

    In your (good) solution will you now get.

    10.000.000 clock periodes with clk_o = '0'
    and
    10.000.000 clock periodes with clk_o = '1'

    (Clock periodes of 50 MHz)

    Your welcome
    jeppe, Dec 12, 2011
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