How to make equal value

[shah_satish2002]

Hi..
I have very basic question..

Here is my code..

Library IEEE;
Use IEEE.std_logic_1164.all;

Entity Del is
port( MTDAT0,MTDAT1,MTDAT2,SEL: in bit;
bit1,Bit2,bit3: out bit);
End Entity Del;

Architecture FA_calc of Del is

begin


process (SEL,MTDAT0,MTDAT1,MTDAT2)

variable IN_vector: bit_vector(3 downto 0);
begin

loop1: for i in 0 to 11 loop

IN_vector := SEL & MTDAT0 & MTDAT1 & MTDAT2 ;

case IN_vector is

when "0000" => bit1<='0'; bit2 <= '0';bit3 <= '0';
when "0100" => bit1<='0'; bit2 <= '0';bit3 <= '0';

when "1100" => bit1<='1'; bit2 <= '0';bit3 <= '0';
when "1110" => bit1<='1'; bit2 <= '0';bit3 <= '0';
when "0110" => bit1<='1'; bit2 <= '1';bit3 <= '0';

when "0010" => bit1<='1'; bit2 <= '1';bit3 <= '0';

when "1010" => bit1<='0'; bit2 <= '1';bit3 <= '0';

when "1011" => bit1<='0'; bit2 <= '1';bit3 <= '0';

when "0011" => bit1<='0'; bit2 <= '1';bit3 <= '1';

when "0111" => bit1<='0'; bit2 <= '1';bit3 <= '1';

when "1111" => bit1<='1'; bit2 <= '1';bit3 <= '1';

when "1101" => bit1<='1'; bit2 <= '1';bit3 <= '1';

when "0101" => bit1<='1'; bit2 <= '0';bit3 <= '1';

when "0001" => bit1<='1'; bit2 <= '0';bit3 <= '1';

when "1001" => bit1<='0'; bit2 <= '0';bit3 <= '1';

when "1000" => bit1<='0'; bit2 <= '0';bit3 <= '1';

End case;

-- SEL <= bit3 ; // Here i want to make value of SEL is equal to bit3

end loop loop1;
end process;

End Architecture FA_calc ;



In my code, I want to make SEL is equal to bit 3 at the end of each loop..so on next cycle, the value of SEL become equal to bit3.

How can i make it.. ??

Thanks..