How to meet timing constraints in an FPGA

[boysr2003]

Hi, my name is Yassir Boukhriss. I am using System generator from Xilinx. I have succesfully integrated a system generator design into a top level VHDL code of a digital receiver running on Virtex II. In the System generator Token i have selected a simulink system period to be a fraction of the period of the blocks of the system generator design. The smaller that fraction the more relaxed the timing constraints of my whole design are. Does that only mean that placing and routing of the whole design will take less time, or does that mean something else too? I'd appreciate it if i could get an answer for that.
Thanks.
Yassir Boukhriss