how to meet timing constraints

Discussion in 'VHDL' started by ra, Oct 8, 2004.

  1. ra

    ra Guest

    Hi all,
    I'm approaching the hardware world (I'm a software engineer), and
    developing a system on a Xilinx FPGA (VirtexIIP) using ISE 6.2. I'd like
    to know if there is a good book or some other source of information
    about what to do if timing constraints are not met (where to look for
    information, how to interpret them, what to change, etc. I have some
    vague ideas, obtained from Xilinx support, but I'm looking for a more
    comprehensive document on the topic.

    Thank You

    RA
    ra, Oct 8, 2004
    #1
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  2. ra

    Barry Brown Guest

    At the Xilinx website, under education, there is a free online training
    class about "Timing Closure Flow". Might be worth a look.


    "ra" <> wrote in message news:r%p9d.209790$D%.148713@attbi_s51...
    > Hi all,
    > I'm approaching the hardware world (I'm a software engineer), and
    > developing a system on a Xilinx FPGA (VirtexIIP) using ISE 6.2. I'd like
    > to know if there is a good book or some other source of information
    > about what to do if timing constraints are not met (where to look for
    > information, how to interpret them, what to change, etc. I have some
    > vague ideas, obtained from Xilinx support, but I'm looking for a more
    > comprehensive document on the topic.
    >
    > Thank You
    >
    > RA
    Barry Brown, Oct 8, 2004
    #2
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  3. ra wrote:


    > about what to do if timing constraints are not met (where to look for
    > information, how to interpret them, what to change, etc.


    Synthesis tools can report the "longest path" to you. They will print an
    information where the path starts and where it ends. Start and end are
    flipflops (or sometimes latches) in most cases.
    Normally these FFs can be identified by their names and one can find
    them in the VHDL source code. Now it is your part to understand, why
    this delay path from the startpoint to the endpoint is so long. (In most
    cases one will have a big bunch of combinational logic.)
    Once you have identified the reason, you can think about a solution
    (pipelining, (functional) easier description of this block...).

    It may be helpful to split a design in some smaller components and
    synthesize them separately. Understanding and finding the delay paths
    may be easier, because you don't have to search them in a huge complex
    block.

    Ralf
    Ralf Hildebrandt, Oct 9, 2004
    #3
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